U5006240458B1
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`US 6,240,458 B1
`(10) Patent N0.:
`(12) Unlted States Patent
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`(45) Date of Patent:
`May 29, 2001
`Gilbertson
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`(54) SYSTEM AND METHOD FOR
`PROGRAMMABLY CONTROLLING DATA
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`TRANSFER REQUEST RATES BETWEEN
`DATA SOURCES AND DESTINATIONS IN A
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`DATA PROCESSING SYSTEM
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`Inventor: Roger Lee Gilbertson, Minneapolis,
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`MN (US)
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`(73) Assignee: Unisys Corporation, Blue Bell, PA
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`(Us)
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`(75)
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`6/1993 Webb, Jr. et a1.
`5,222,223 *
`9/1996 Guttag et 211.
`595609030 *
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`3/1999 Abriu ................................... 370/413
`5,881,065 *
`6,138,192 * 10/2000 Hausauer
`............................. 710/100
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`* cited by examiner
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`Primary Examiner—Ario Etienne
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`(74) Attorney, Agent, or Firm—Charles A. Johnson; Mark
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`T~ Starr; Altera Law Group
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`(57)
`ABSTRACT
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`A system and method for selectively controlling the inter-
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`face throughput of data transfer requests from request
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`sources to request destinations. The system and method
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`provide a manner in Which the flow of data transfer requests
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`from request sources to request destinations are controlled.
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`The data transfer requests from each of the request sources
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`are temporarily stored for future delivery to its addressed
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`request destination. Delivery of the stored data transfer
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`requests to the addressed request destination is enabled
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`according to a predetermined delivery priority scheme.
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`Certain Stored data tranSfer requeStS are identified to be
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`selectively suspended from being prioritized and delivered
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`to the addressed request destination. The identified data
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`transfer requests are suspended from delivery for a definable
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`period of time. Upon expiration of the definable period of
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`time, the suspended data transfer requests, as well as all
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`other stored data transfer requests, are enabled for prioriti-
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`zation and delivery in accordance With the predetermined
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`delivery priority scheme.
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`33 Claims, 14 Drawing Sheets
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`( * ) N09963:
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`Subjectto any disclaimer, the term Of this
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`patent 15 extended or adjusted under 35
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`U-S-C- 154(b) by0 days.
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`(21) Appl. No.: 09/218,211
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`(22)
`Flled:
`Dec. 22’ 1998
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`(51)
`Int. Cl.7 ...................................................... G06F 15/16
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`(52) us. Cl.
`.......................... 709/232, 709/233, 709/234,
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`709/235; 710/39; 710/60
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`(58) Field of Search ..................................... 709/234, 200,
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`709/222, 252, 243, 207, 238, 235, 232,
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`233’ 240; 710/263, 264, 244’ 112’ 116,
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`39, 40, 52, 58—60; 711/150, 151; 370/395,
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`414
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`(56)
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`References Cited
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`U~S- PATENT DOCUMENTS
`1/1985 Agrawal et a1.
`4,493,021 *
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`5,136,718 *
`8/1992 Haydt .
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`110
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`__________________________________ ‘
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`110A
`110B
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`SYMMETRICAL MULTIPROCESSING PLATFORM
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`INTEL - 1007
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`INTEL - 1007
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`US. Patent
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`May 29, 2001
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`Sheet 1 0f 14
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`US 6,240,458 B1
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`US. Patent
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`May 29, 2001
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`US. Patent
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`May 29, 2001
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`Sheet3 0f14
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`US 6,240,458 B1
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`US. Patent
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`May 29, 2001
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`US 6,240,458 B1
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`US. Patent
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`May 29, 2001
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`Sheets 0f14
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`US 6,240,458 B1
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`US. Patent
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`May 29, 2001
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`Sheet 6 0f 14
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`US. Patent
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`May 29, 2001
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`Sheet7 0f14
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`US 6,240,458 B1
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`US. Patent
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`Sheet 8 0f 14
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`US. Patent
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`May 29, 2001
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`Sheet 9 0f 14
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`US 6,240,458 B1
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`US. Patent
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`May 29, 2001
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`Sheet10 0f14
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`US 6,240,458 B1
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`
`
`
`
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`
`
`INTEL - 1007
`
`INTEL - 1007
`
`

`

`
`US. Patent
`
`
`
`
`May 29, 2001
`
`
`
`
`
`Sheet 11 0f 14
`
`
`
`US 6,240,458 B1
`
`
`
`1188 AB STRESS f “00
`HOLD [7:0]
`
`
`
`
`
`
`
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`
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`
`
`1190
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`FIG. 11
`
`INTEL - 1007
`
`INTEL - 1007
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`

`

`
`US. Patent
`
`
`
`
`May 29, 2001
`
`
`
`
`Sheet 12 0f 14
`
`
`
`US 6,240,458 B1
`
`IDENTIFY DESTINATION RESOURCES
`
`
`
`
`
`
`
`
`
`
`
`
`CONFIGURE MODE REGISTERS FOR EACH
`
`
`
`DESTINATION RESOURCE
`
`
`
`
`
`
`
`
`
`SELECT MASKING WAVEFORM BASED ON
`
`
`
`
`CONFIGURED MODE FOR EACH
`
`
`
`DESTINATION RESOURCE
`
`
`
`REMOVAL ACTIVITY
`
`
`
`
`SELECT ONE OR MORE DESTINATION
`
`
`RESOURCES TO SUSPEND REQUEST
`
`
`
`
`
`
`
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`
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`SUSPEND REQUEST REMOVAL ACTIVITY
`
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`FOR SELECTED DESTINATION
`
`
`RESOURCES ACCORDING TO
`
`
`
`
`RESPECTIVE MASKING DUTY CYCLES
`
`
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`
`
`1 200
`
`
`
`1 202
`
`
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`1 204
`
`
`
`1 206
`
`
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`1208
`
`
`
`
`FIG. 12
`
`INTEL - 1007
`
`INTEL - 1007
`
`

`

`
`US. Patent
`
`
`
`
`May 29, 2001
`
`
`
`
`Sheet 13 0f 14
`
`
`
`US 6,240,458 B1
`
`
`
`
`
`
`
`
`
`
`
`
`FIRST POD ASSIGNED TO ROUTINELY
`
`
`
`
`PERFORM LONG DATA TRANSFER
`
`
`
`
`OPERATIONS TO DESTINATION
`
`
`
`RESOURCE A INITIATES DATA
`
`TRANSFER
`
`
`
`
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`
`
`
`
`1 300
`
`
`
`
`
`
`
`
`
`
`
`
`
`I/O MODULE
`
`
`
`ASSOCIATED WITH
`
`
`
`
`
`ENABLE FIRST POD TO
`
`
`
`
`SECOND POD INITIATE
`
`
`
`
`
`INITIATE ANOTHER DATA
`
`
`
`DATA TRANSFER TO
`
`
`
`
`TRANSFER
`
`DESTINATION
`
`RESOURCE A?
`
`
`
`
`
`
`
`
`
`
`
`
`I/O DATA
`,
`
`
`TRANSFER HAVE
`
`
`
`
`ASSOCIATED TIMEOUT
`
`
`
`RESTRICTION
`7
`
`
`
`
` 1 306
`
`
`
`YES
`
`
`
`
`
`
`
`DYNAMICALLY SCAN DESIRED
`
`
`
`MODE INTO PROGRAMMABLE
`
`
`REGISTER CORRESPONDING TO
`
`
`FIRST POD
`
`SELECTED MODE
`
`
`
`
`DISABLE FURTHER DATA
`
`
`
`
`TRANSFERS FROM FIRST POD TO
`
`
`DESTINATION RESOURCE A FOR
`PERIOD DESIGNATED BY
`
`
`
`
`
`
`FIG. 13
`
`
`1310
`
`INTEL - 1007
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`INTEL - 1007
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`

`

`
`US. Patent
`
`
`
`
`May 29, 2001
`
`
`
`
`Sheet 14 0f 14
`
`
`
`US 6,240,458 B1
`
`
`
`
`
`
`ENABLE A SELECTED ONE OF THE STORE/FETCH
`
`
`
`
`
`QUEUES TO INITIALIZE THE CORRESPONDING MSU
`
`
`
`
`PRELOAD A NUMBER OF STORE/FETCH REQUESTS
`
`
`
`INTO REMAINING STORE/FETCH QUEUES OF
`
`
`CORRESPONDING MSU
`
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`SET INDEFINITE DATA TRANSFER BLOCK ON
`
`
`REMAINING STORE/FETCH QUEUES
`
`1 400
`
`
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`1402
`
`
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`1404
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`
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`START MSU CLOCKS
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`1406
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`
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`EXECUTE MSU INITIALIZATION SEQUENCE
`
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`DYNAMICALLY SCAN BLOCK RELEASE INTO PROGRAMMABLE
`
`
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`REGISTERS CORRESPONDING TO DESTINATION RESOURCE OF
`
`
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`REMAINING STORE/FETCH QUEUES
`
`1410
`
`
`
`1408
`
`
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`
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`RELEASE PRELOADED REQUESTS TO DOWNLINE MSU
`
`
`LOGIC STRUCTURES
`
`
`
`1412
`
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`USER-DEFINED
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`TIME PERIOD EXPIRE
`
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`?
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`YES
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`
`STOP MSU CLOCKS
`
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`ASCERTAIN MSU STATE
`
`
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`NO
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`COMPARE ACTUAL MSU STATE TO
`
`
`
`EXPECTED MSU STATE
`
`FIG. 14
`
`1414
`
`
`
`
`
`1416
`
`
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`1418
`
`
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`
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`1420
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`
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`INTEL - 1007
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`INTEL - 1007
`
`

`

`
`
`US 6,240,458 B1
`
`
`1
`SYSTEM AND METHOD FOR
`
`
`
`PROGRAMMABLY CONTROLLING DATA
`
`
`
`TRANSFER REQUEST RATES BETWEEN
`
`
`
`
`DATA SOURCES AND DESTINATIONS IN A
`
`
`
`
`DATA PROCESSING SYSTEM
`
`
`
`CROSS-REFERENCE TO OTHER PATENT
`
`
`APPLICATIONS
`
`
`
`
`
`
`
`
`
`
`
`The following co-pending patent application of common
`
`
`
`
`
`assignee contains some common disclosure:
`
`
`
`
`
`
`
`“Multi-Level Priority Control System And Method For
`
`
`
`
`
`
`Managing Concurrently Pending Data Transfer Requests”,
`
`
`
`
`
`
`
`
`filed concurrently herewith with assigned Ser. No. 09/218,
`
`
`
`
`
`
`377, which in incorporated by reference in its entirety;
`
`
`
`
`
`
`
`“Transfer Request Selection Method And Apparatus For
`
`
`
`
`
`Symmetrical Multiprocessor Systems”, filed concurrently
`
`
`
`
`
`
`
`
`herewith with assigned Ser. No. 09/218,210, which is incor-
`
`
`
`
`
`porated by reference in its entirety; and
`
`
`
`
`
`
`
`“Queueing Architecture And Control System For Data
`
`
`
`
`
`Processing System Having Independently-Operative Data
`And Address Interfaces”, Ser. No. 09/096,822, filed Jun. 12,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1998, which is incorporated herein by reference in its
`
`entirety.
`
`FIELD OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`This invention relates generally to data transfer request
`
`
`
`
`
`
`
`management in data processing systems, and more particu-
`
`
`
`
`
`
`
`
`larly to an interface and programmable interface control
`
`
`
`
`
`
`
`
`system and method for selectively providing, and control-
`
`
`
`
`
`
`
`
`
`ling the rate of, data transfer requests to destination
`
`
`
`
`
`
`
`
`resources, thereby providing the ability to manipulate data
`
`
`
`
`
`
`
`throughput under normal operating conditions, and to pro-
`
`
`
`
`
`
`vide a means for performing transaction processing testing.
`BACKGROUND OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`Data processing systems generally include multiple units
`
`
`
`
`
`
`
`such as processing units, memory units, input/output units,
`and the like, which are interconnected over one or more
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`system interfaces. The interfaces provide for the transfer of
`
`
`
`
`
`
`
`
`
`digital signals between the units. Since many of the opera-
`
`
`
`
`
`
`
`
`tions within data processing systems involve such transfers,
`
`
`
`
`
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`
`
`the efficiency of the interfaces has a major impact on the
`
`
`
`
`
`
`overall performance of the data processing system.
`
`
`
`
`
`
`
`Many conventional interfaces used within data processing
`
`
`
`
`
`
`
`
`systems have several types of signal lines, including data
`
`
`
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`
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`
`
`lines for transferring data signals, and address lines for
`
`
`
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`
`
`transferring address signals. The address lines generally
`
`
`
`
`
`
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`
`
`provide information indicative of the type of request, and
`indicate a unit and/or a particular addressable
`further
`
`
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`
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`resource associated within the unit that is involved with the
`
`
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`request. The data lines provide data signals which are
`
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`
`
`associated with the request.
`
`
`
`
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`
`
`Requests for data transfers may occur at a faster rate than
`
`
`
`
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`
`
`the memory and associated cache coherency logic can
`
`
`
`
`
`
`
`sustain. A buffering technique may be used to queue such
`
`
`
`
`
`
`
`
`requests until they can be processed. However, the queuing
`function can sometimes result in inefficient and discrimina-
`
`
`
`
`
`
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`
`
`
`
`
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`tory request servicing.
`In some cases, one processor’s
`
`
`
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`
`
`requests may be repeatedly processed, while another’s are
`
`
`
`
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`
`
`left relatively unattended. In other cases, a processor having
`
`
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`
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`relatively few requests may needlessly tie up system
`
`
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`
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`resources by receiving unnecessary request service polls.
`
`
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`
`These situations can reduce available request bandpass, and
`
`
`
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`
`
`increase the probability of request stalling or request lock-
`
`
`
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`
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`
`
`out. To address this issue,
`the buffering technique may
`
`
`2
`
`
`
`
`
`
`
`
`include a priority scheme to output the data transfer requests
`
`
`
`
`
`
`
`according to a priority assigned to each of the data transfer
`
`
`
`
`
`
`
`
`requests. One priority scheme known in the art is known as
`
`
`
`
`
`
`
`
`a “fixed” request priority scheme. Each requester is assigned
`
`
`
`
`
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`
`
`a fixed priority value, and requests are handled according to
`
`
`
`
`
`
`
`
`this associated priority value. Those requests having a high
`
`
`
`
`
`
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`
`
`fixed priority value are always handled prior to those having
`
`
`
`
`
`
`
`relatively low priority values. Another request priority
`
`
`
`
`
`
`
`scheme is referred to as “snap-fixed”, where input request
`
`
`
`
`
`
`activity is continually or periodically polled. This results in
`
`
`
`
`
`
`
`a captured “snapshot” of the request activity at a given time.
`
`
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`
`All of the captured requests are processed in a fixed order
`
`
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`
`until all requests in the snapshot have been processed, at
`
`
`
`
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`
`
`which time a new snapshot is taken. A “simple rotational”
`
`
`
`
`
`
`
`priority scheme involves changing the requester priority on
`
`
`
`
`
`
`
`
`
`a periodic basis. For example, the requester priority may be
`
`
`
`
`
`
`changed whenever a request is granted priority. Requester
`
`
`
`
`
`
`
`
`(N—1) moves to priority level (N), requester (N) moves to
`
`
`
`(N+1), and so forth.
`
`
`
`
`
`
`
`
`Regardless of the priority scheme used, there may be
`
`
`
`
`
`
`
`times when the implemented priority scheme inhibits execu-
`
`
`
`
`
`
`
`tion of a desired system operation. For example, testing of
`
`
`
`
`
`
`
`a complex multiprocessing system having multiple data
`
`
`
`
`
`
`
`
`transfer sources and multiple data transfer destinations can
`
`
`
`
`
`
`
`be incredibly complicated, particularly where test programs
`must be written to simulate transaction “stress” situations.
`
`
`
`
`
`
`
`
`
`
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`
`
`
`Such a transaction stress situation may occur during normal
`
`
`
`
`
`
`
`operation where some resources, like memory, are suddenly
`
`
`
`
`
`
`
`
`inundated with pending data transfer requests. When this
`
`
`
`
`
`
`
`
`occurs, memory response times may be reduced, causing the
`
`
`
`
`
`
`
`
`data transaction queues to fill. The requesting modules must
`
`
`
`
`
`
`
`
`
`be able to accommodate this situation to avoid queue
`
`
`
`
`
`
`
`overrun problems, and it is therefore important to be able to
`simulate and test
`these conditions. Further,
`the memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`resources must be able to manage and absorb the high
`
`
`
`
`
`
`
`
`volume of sudden request traffic and properly respond to the
`
`
`
`
`
`
`
`requesting modules. Again, these situations require thorough
`
`testing.
`
`
`
`
`
`
`
`In order to prepare test programs to simulate these stress
`conditions, a detailed knowledge of the entire hardware
`
`
`
`
`
`
`
`
`
`
`implementation would be required in order to predict the
`
`
`
`
`
`
`direct effect on system hardware produced by test program
`
`
`
`
`
`
`
`stimulus. The time, required resources, complexity and cost
`
`
`
`
`
`
`of preparing such test programs is prohibitive.
`It would therefore be desirable to provide an efficient
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`arrangement and method that allows data transfer request
`
`
`
`
`
`
`
`queues to be controlled, or “throttled”, by way of simple
`
`
`
`
`
`
`user-defined parameters. Implemented priority schemes can
`
`
`
`
`
`
`
`be maintained, but can be selectively bypassed to perform
`stress tests, or to accommodate peculiar situations which
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`might arise during normal operation. The present invention
`
`
`
`
`
`
`
`
`provides such a solution, and provides these and other
`
`
`
`
`
`
`
`advantages and benefits over the prior art.
`SUMMARY OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`The present invention relates to a system and method for
`
`
`
`
`
`
`
`selectively controlling the interface throughput of data trans-
`
`
`
`
`
`
`
`fer requests from request sources to request destinations,
`
`
`
`
`
`
`
`thereby providing the ability to manipulate data throughput
`
`
`
`
`
`
`
`under normal operating conditions, and to provide a means
`
`
`
`
`
`for performing transaction processing testing.
`In accordance with one embodiment of the invention, a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`method is provided for controlling the flow of data transfer
`
`
`
`
`
`
`
`requests from various request sources to various request
`
`
`
`
`
`
`
`destinations. Each data transfer request is a request for an
`
`
`
`
`
`
`
`addressed one of the request destinations to supply a data
`
`
`
`
`
`
`
`10
`
`15
`
`
`
`20
`
`25
`
`
`
`30
`
`35
`
`
`
`40
`
`
`
`45
`
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`
`INTEL - 1007
`
`INTEL - 1007
`
`

`

`
`
`US 6,240,458 B1
`
`
`3
`
`
`
`
`
`
`
`
`segment to the requesting source. The data transfer requests
`
`
`
`
`
`
`
`
`
`from each of the request sources are temporarily stored for
`
`
`
`
`
`
`
`future delivery to its addressed request destination. Delivery
`
`
`
`
`
`
`
`
`of the stored data transfer requests to the addressed request
`
`
`
`
`
`destination is enabled according to a predetermined delivery
`
`
`
`
`
`
`
`
`priority scheme. Certain ones of the stored data transfer
`
`
`
`
`
`
`
`
`requests are identified to be selectively suspended from
`
`
`
`
`
`
`
`
`being prioritized and delivered to the addressed request
`
`
`
`
`
`
`
`
`destination. These identified data transfer requests are sus-
`
`
`
`
`
`
`
`
`pended from delivery for a definable period of time. During
`
`
`
`
`
`
`
`
`this time, the destination addressed by the suspended data
`
`
`
`
`
`
`
`
`
`transfer requests will not receive any of these requests. Upon
`
`
`
`
`
`
`
`
`
`expiration of the definable period of time, the suspended
`
`
`
`
`
`
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`data transfer requests, as well as all other stored data transfer
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`requests, are enabled for prioritization and delivery in accor-
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`dance with the predetermined delivery priority scheme. In
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`this manner, the suspended data transfer requests will gain
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`priority during the period of suspension, and will thereafter
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`be provided to the destination according to their respective
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`priorities.
`In accordance with another embodiment of the invention,
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`a method is provided for controlling the flow of data transfer
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`requests during normal system operations of a multiprocess-
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`ing computing system that has multiple request sources that
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`provide data transfer requests to multiple request destina-
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`tions. The data transfer requests are prioritized according to
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`a predetermined request dispatch priority scheme. Each data
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`transfer request is a request for an addressed one of the
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`request destinations to supply a data segment to a respective
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`one of the request sources. The method includes periodically
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`performing first data transfer operations between a first
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`request source and a targeted request destination. A second
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`data transfer operation is initiated between a second request
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`source and the targeted request destination, wherein the
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`second data transfer operation is subject
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`limitation. The first data transfer operations are
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`suspended for a user-defined period upon recognition of
`initiation of the second data transfer operation, and the
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`second data transfer operations are enabled during the
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`user-defined period. Upon expiration of the user-defined
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`period, both the first and second data transfer operations are
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`enabled in accordance with the predetermined request dis-
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`patch priority scheme.
`In accordance with yet another embodiment of the
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`invention, a method is provided for controlling the flow of
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`data transfer requests during offline testing of a multipro-
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`cessing computing system having a plurality of request
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`sources capable of providing data transfer requests to a
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`plurality of request destinations in accordance with a pre-
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`determined request dispatch priority scheme. The multipro-
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`cessing computing system including a main storage unit
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`having multiple data transfer queues that operate in parallel
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`to temporarily store the data transfer requests from the
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`request sources to the request destinations. The method
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`includes selecting a first of the plurality of data transfer
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`queues to initialize the memory in the main storage unit. A
`number of known data transfer requests are loaded into
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`second ones of the plurality of data transfer queues, wherein
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`the second ones of the data transfer queues comprise at least
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`one of the remaining ones of the data transfer queues not
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`selected to initialize the memory. Data transfer operations
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`are prohibited from the second data transfer queues for a
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`user-defined period. A memory initialization sequence is
`executed via the first data transfer queue. The data transfer
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`operations are enabled from the second data transfer queues
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`upon expiration of the user-defined period.
`In accordance with another aspect of the invention, a data
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`transfer request interface circuit is provided for use in a
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`request source to provide data transfer requests to at least
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`one request destination. The interface circuit
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`queuing circuit coupled to each of the request sources to
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`receive and temporarily store the data transfer requests. A
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`priority logic circuit is coupled to the queuing circuit to
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`prioritize a sequence by which the stored data transfer
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`requests are output from the queuing circuit. The priority
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`logic operates in accordance with a predetermined priority
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`algorithm. A masking register is coupled to the priority logic
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`circuit to mask predetermined stored data transfer requests
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`from being considered by the priority logic circuit
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`response to a masking signal pattern provided to the mask-
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`ing register. In this manner, the predetermined ones of the
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`stored data transfer requests are retained in the queuing
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`circuit while the remaining stored data transfer requests are
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`allowed to be prioritized and output from the queuing
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`circuit. A configurable request flow controller is coupled to
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`the masking register to generate the masking signal pattern
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`in response to user-defined parameters. The user-defined
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`parameters define at least which of the stored data transfer
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`requests are to be masked by the masking register, and the
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`duration to which the masking signal pattern is to be
`sustained.
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`Still other objects and advantages of the present invention
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`will become readily apparent to those skilled in this art from
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`the following detailed description. As will be realized, the
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`invention is capable of other and different embodiments, and
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`its details are capable of modification without departing
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`from the scope and spirit of the invention. Accordingly, the
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`drawing and description are to be regarded as illustrative in
`nature, and not as restrictive.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The invention is described in connection with the embodi-
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`ments illustrated in the following diagrams.
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`FIG. 1 is a block diagram of a Symmetrical Multi-
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`Processor (SMP) System Platform in which the principles of
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`the present invention may be applied;
`FIG. 2 is a block diagram of one embodiment of a
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`Memory Storage Unit (MSU);
`FIG. 3 is a block diagram of bi-directional MSU Interface
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`(MI) and associated interface control logic;
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`FIG. 4A is a timing diagram of a POD-to-MSU address
`transfer;
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`FIG. 4B is a timing diagram of a POD-to-MSU data
`transfer;
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`FIG. 5 is a block diagram of one embodiment of the
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`Address Queue Logic;
`FIG. 6 is a block diagram of one embodiment of the Data
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`Valid Routing Logic;
`FIG. 7 is a block diagram of one embodiment of the
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`Store/Fetch Queue Logic;
`FIG. 8 is a block diagram of one embodiment of a
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`Memory Cluster depicting the various destination resources
`contained therein;
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`FIG. 9 is a block diagram of one embodiment of an MSU
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`illustrating the availability of PODs being the resource
`destination;
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`FIG. 10 is a block diagram illustrating one manner of
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`configurably controlling the flow of data transfer requests to
`particular destination resources in accordance with the
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`present invention;
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`FIG. 11 is a schematic diagram illustrating one embodi-
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`ment of a Configurable Request Flow Controller in accor-
`dance with the present invention;
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`INTEL - 1007
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`INTEL - 1007
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`

`

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`US 6,240,458 B1
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`FIG. 12 is a flow diagram illustrating one embodiment of
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`a method for programmably controlling the flow of data
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`transfer requests in accordance with the present invention;
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`FIG. 13 is a flow diagram of an example procedure used
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`during normal operation of the system using the principles
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`of the present invention; and
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`FIG. 14 is a flow diagram of an example procedure used
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`during offline testing of the system using the principles of
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`the present invention.
`DETAILED DESCRIPTION OF THE
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`ILLUSTRATED EMBODIMENTS
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`Generally, the present invention provides a system and
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`method for controlling the throughput of data transfer
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`requests through a source-to-destination interface. The
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`invention provides programmable control of the removal of
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`data transfer requests from queuing structures to destination
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`resources such as memory, and further provides for control
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`of the rate at which requests are removed from the queuing
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`structures, including a complete suspension of data transfers
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`for a user-defined period. Control of request removal rates is
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`dynamically configurable, allowing flexibility and ease of
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`use. The present invention facilitates stress testing of both
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`the requester and request receiv