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`US. DEPARTMENT OF COMMERCE
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`UTILITY PATENT APPLICATION
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`TRANSMITTAL LETTER UNDER 37
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`C.F.R. 1.53(b)
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`Eunice Kim
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`I hereby certify that this correspondence is being electronically
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`transmitted to the United States Patent and Trademark Office via the
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`Ofiice electronic filing system on
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`Date. November 4, 2011
`Signature: lEunice Kim/
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`Commissioner for Patents
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`Transmitted herewith for filing is the patent application of
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`Inventor(s):
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`Martin VORBACH; Frank MAY; Dirk REICHARDT; Frank LIER;
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`Gerd EHLERS; Armin NUCICEL; Volker BAUMGARTE; Prashant
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`RAO and Jens OERTEL
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`For:
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`LOGIC CELL ARRAY AND BUS SYSTEM
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`Enclosed are:
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`15 sheets of specification, 5 sheet of claims and 1 sheet of abstract;
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`11 sheets of drawings;
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`Preliminary Amendment;
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`Information Disclosure Statement with List of References;
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`lSt Litigation Information Disclosure Statement with List of References;
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`2“d Litigation Information Disclosure Statement with List of References;
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`Declaration (copy from prior application (37 CFR 1.63(d)); and
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`‘ Appointment of Power of Attorney (including 3.73 (b) Statement).
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`2.
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`copy of the oath or declaration is supplied under paragraph 1G above, is considered as being part
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`of the disclosure of the accompanying application and is hereby incorporated by reference
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`3 .
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`Continuing and Priority Application Information:
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`This application is continuation of and claims priority to US. Patent Application Serial
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`No. 12/371,040, filed on February 13, 2009, which is a continuation of and claims priority to
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`US. Patent Application Serial No. 10/398,546, filed January 20, 2004 (now US. Patent
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`7,5 95,65 9), which is the National Stage of International Patent Application Serial No.
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`PCT/EP01/11593, filed on October 8, 2001, the entire contents of each of which are expressly
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`incorporated in the accompanying application by reference.
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`Page 1
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`INTEL - 1004
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`The filing fee has been calculated aS shown below:
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`BASIC FEE (smafi mum — 95-00(c-fl1ing)
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`L-."""Additional fee for specification and drawings filed in paper over 100 sheets (excluding sequence listing or
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`computer program listing filed in an electronic medium), The fee is $250 for each additional 50 sheets of paper
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`or fraction thereof.
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`Ifthe applicant is a small entity under 37 C.F.Ri §§ 1.9
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`and 1.27, then divide total fee b 2, and enter amount here.
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`5.
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`Please charge the required application filing fee of $1,955.00 to deposit account number
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`Dated: November 4 2011
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`By:
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`Customer No. 26646
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`Respectfully submitted,
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`/Aaron Grunberger/
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`Aaron Grunberger
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`(Reg. No. 59,210)
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`KENYON & KENYON
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`Page 2
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`INTEL - 1004
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`INTEL - 1004
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`METHOD AND DEVICE
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`[2885/158]
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`Field Of The Invention
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`The present invention relates to logic cell arrays.
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`Background Information
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`Logic cell arrays, such as, for example, reconfigurable logic cell arrays include, as particular
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`types, systolic arrays, neuronal networks, multi—processor systems, processors having a
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`number of arithmetic—logic units, and/or logic cells and/or communicative/peripheral cells
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`(I/O), networking and/or network chips, such as crossbar switches, as well as FPGA, DPGA,
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`Xputer, Chameleon chips, etc. The following patents commonly assigned to the assignee of
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`the present application describe logic cell arrays and are incorporated by reference in their
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`entirety: German Patent No. 44 16 881; Gennan Patent No. 197 81 412; German Patent No.
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`197 81 483; German Patent No. 196 54 846, German Patent No. 196 54 593; German Patent
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`No. 197 04 044; German Patent No. 198 80 129, German Patent No. 198 61 088, German
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`Patent No. 199 80 312; International Patent Application No. PCT/DE 00/01869; German
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`Patent No. 100 36 627, German Patent No. 100 28 397, German Patent No. 101 10 530,
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`German Patent No. 101 11 014, International Patent Application No. PCT/EP 00/ 10516, and
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`European Patent No. 01 102 674. According to their wide variety, logic cells are herein
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`defined as any cells that contain logic, arithmetic, switches, memory, or peripherals.
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`In systems such as those previously cited, there are approaches that enable in efficient
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`processing of data which may be implemented in hardware architectures. There nevertheless
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`exists in practical implementations the need to optimize designs, which, in particular, can be
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`structured in a space-saving manner on a wafer and]or can be operated in an energy~saving
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`manner. Additionally, it is desirable to find especially advantageous kinds of operation.
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`One of the difficulties with conventional systems is that a large number of cells have to
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`communicate with each other. The communication may be required in order to pass the data
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`to be processed from one cell to another. This is the case, for example, if a cell is supposed to
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`fin‘ther process the results from another cell, e. g., by linking of the result obtained there to
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`results obtained from one or more other cells. Furthermore, communication may be required
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`to transmit status signals.
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`Busses for transmitting signals to one of a number of possible receivers have been used in
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`this context. Busses are bundles of wires, the number of wires typically being determined
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`from the number of bits to be transmitted together, that is, typically in parallel, ‘plus in some
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`NYO 2236558V1
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`With conventional simple busses, as are used, for example, in PC's for the communication of
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`plug—in boards with the CPU and/or with each other, the bus lines may be routed to all
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`receivers, and then appropriate control signals transmitted along with them, that is,
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`addressing, ensures that only those receivers respond that are supposed to receive the data.
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`Such a system becomes problematic when a great many communicating units need access to
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`the bus or busses. This is because the communication of data must wait, if necessary, until the
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`bus has been released by other units and]or time-slice solutions must be implemented that
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`grant a transmitting unit only a certain transmission time, which as a rule is independent of
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`whether all data has been transmitted in this time, which might also make it necessary to use
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`a number of time slices for the data transmission. For example, this approach is practiced in
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`systems like the token ring network. In systems like logic cell arrays, in which very rapid
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`communication is desired in order to ensure high data processing speeds, this is an
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`It has also been proposed that the busses be segmented. If, for example, in a series of logic
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`cells several units to be connected to each other are disposed close together in pairs, a bus
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`line that passes along all units and consequently is long may be separated by means of
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`switches in order to form several subbus systems. In this context, each segment, like the
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`entire bus, comprises the required number of parallel data lines and the additionally required
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`protocol lines; the communication of a pair of logic cells that are disposed close together does
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`not disrupt the communication of another pair that are disposed close together. In this way,
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`the data rate that is transmitted via the bus system may be substantially increased.
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`However, this system may not work well when integrated on semiconductor chips, such as in
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`CMOS technology, where the structure is typically complex and the operation is energy
`inefficient.
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`Summary
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`According to example embodiments of the present invention, in a logic cell array having a
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`number of logic cells and a segmented bus system for logic cell communication, the bus
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`system includes different segment lines having shorter and longer segments for connecting
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`two points in order to be able to minimize the number of bus elements traversed between
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`separate communication start and end points.
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`By configuring the busses using segments of great length that are fashioned as a single line
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`for bypassing long paths in a logic cell array, an especially simple design and an especially
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`efficient operation result. By simultaneously providing short segment lines, it is ensured that
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`all points are addressable as needed.
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`Each of the segment lines may be formed of a plurality of parallel lines whose number is
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`determined by the bus width and/or the bus protocol. Each segment is therefore formed by a
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`' bundle of parallel lines. All lines of a segment may have the same length, so that the lines of
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`a line bundle may all be routed to one and the same end point line, such as a data input of a
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`logic cell, where they may be connected to the input members that are assigned to each of
`their bits.
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`According to one example embodiment, data conversion logic cells like arithmetic units have
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`three of the line bundles that are required for the processed bit width to be supplied to them as
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`data supply lines. This permits carrying out a linking of operands A, B, C of the AxB+C type
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`within the cell. This operation is of particular significance in the field of digital signal
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`processing, and the bus structure is therefore especially suitable for logic cell arrays for the
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`construction of real-time configurable DSP arrays.
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`According to another example embodiment, a logic cell array can perform arithmetically
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`multiplicative linking of operands if at least two of the line bundles for data for the bit Width
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`being processed are led out from the cells, in particular with one line bundle for high-order
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`bits and one line bundle for low—order bits. In this way, for a data word width of 32 bits, a 64-
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`bit—wide output is created. in order to output the result of a multiplication in full width.
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`In reconfigurable logic cells, control inputs may be addressable in particular via the
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`segmentable bus system and are disposed in such a manner that at least the logic cell's
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`sequence control signals, such as the signals Reset, Step, Stop, Go and Reload, are
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`transferable into the cell. These trigger and/or enable a reset, a reconfiguration and an
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`activation, respectively. For this purpose a corresponding number of bit lines may be
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`provided. In one embodiment, at least two bit-wide data lines are therefore provided for
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`control signal inputs. Each of the control signals may haVe a separate signal input assigned to
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`it. Alternatively, an input linking circuit on a several~bit-wide status line may provide for an
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`orderly addressing of the cell. These signal inputs are control signal inputs that can carry the
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`signals that control configuration and/or reconfiguration (flow control signals), such as
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`trigger signals. The actual communication of the cell with the unit or a reconfiguring unit,
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`such as a configuration manager (CT or CM) may thus be achieved by techniques, for
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`example, via the so—called ready/ack/rej protocol, which permits a reconfiguration of the cell
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`only under certain conditions. For the details of this protocol, reference is made to the above-
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`listed patents and additional publicly accessible documents about XPP/VPU architecture.
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`In the case of rebooting. The bus structure may be designed for this accordingly.
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`Furthermore, the bus system may be routed to I/O interfaces and/or to external data
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`memories. In other words,.the segmentation structure may be used to advantage both inside
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`and outside the logic cell field. I/O interfaces transmit fiom bus systems that are inside chips
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`to the outside. In this context any bus systems, in some cases alternating in time, are
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`connected for external output and/or input. In addition, the possibility may exist of combining
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`several bus systems in such a manner that they are synchronized with each other. For
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`example, any two output bus systems or an input bus and an output bus together may be
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`In an example embodiment of the bus system, a series of interline elements is provided. Here
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`“line” indicates in particular a first—class conductor, such as a continuous metal line within a
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`semiconductor wafer. “Interline elements” indicate those elements that are disposed between
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`any two lines that are assigned to each other. Interline elements may be connecting switches,
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`in particular the control arrangements that respond to the requirements of logic cells and/or
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`the communication thereof and/or other units; thus, the switch may, for example, open or
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`close at the request of a configuration manager, that is, a unit that configures the logic cell
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`field. This makes it possible to use a compiler to establish how the bus structure is to be
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`designed. In particular the compiler or another configuring or controlling unit is able to
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`determine whether the communication between two cells that are separated is to be
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`accomplished via segment lines having shorter or longer segments, and moreover, if there are
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`a number of longer segments, a preference may also be- specified through which one of a
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`multiplicity of segment lines the communication is to occur. In this way, the power loss
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`through the switch may be minimized and/or an optimal adaptation of the data conversion
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`and/or processing to signal propagation times may be provided along the bus lines.
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`The interline elements may additionally or alternatively include multiplexers in order to feed
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`a signal from a line to one of a series of destinations, such as logic cells, and/or lines that
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`continue further and feed the signal to a multiplicity of destinations, in particular selectable
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`destinations, simultaneously.
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`Furthermore, registers may be provided as interline elements. These perform different tasks.
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`In this manner data may at first be kept on the bus until a destination is ready to retrieve
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`them. Furthermore, when busses are very long, data processing can be prevented from being
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`properly completed if the long periods of time until the data arrive at the destination when
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`paths are long and (in some cases) the return of the reception confn'mation is taken into
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`account. Buffering the data in registers increases the total amount of time (delay) until a data
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`packet traverses the bus, but the interim time until arrival of the data (latency) in which the
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`array or individual cells may not be used meaningfully is reduced. A tradeoff between latency
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`and delay may be required, in which the register is switched in, for example, only under
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`predetermined and/or established conditions, such as very long bus paths. It may then be
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`advantageous if the switching on of the register is controlled, e.g., by a control unit or similar
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`Page 6 of 362
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`INTEL - 1004
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`item, like a configuration manager, which in turn is able to operate in response to compiler-
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`generated commands. Furthermore, it may be advantageous to provide a register in order to
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`ensure a synchronous arrival of bits of different significance at a destination point. If busses
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`are fed back, that is, a connection is provided from a cell output to the input of the same cell,
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`registers may be used in such high—frequency feedback loops, to prevent damage to
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`components by the register—imposed delay time.
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`In a particular implementation, registers may be designed all or in part as additive and/or
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`multiplicative registers; specific links may be implemented without problem and with little
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`circuitry effort, and, thus, the logic cell structure may be relieved on a net basis via shifting of
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`simple linking tasks. In particular, a register may be designed precisely for the purpose of
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`linking two operands algebraically; in busses for transmitting status signals that indicate the
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`status of a logic cell or a series of logic cells and/or trigger a change thereof, that is, in busses
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`for so-called trigger vectors, the registers may preferably be designed to implement Boolean
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`links and/or lookup tables, such as modifiable lookup tables.
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`Line drivers can also be provided as interline elements.
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`This may be necessary in particular for multiplex systems that provide a very strong signal
`fanout.
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`In another example embodiment of the present invention, it is possible to provide a change
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`from one segment line having longer segments to a segment line having shorter segments
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`and/or vice-versa along a data transmission path. This permits the provision of roughly equal
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`signal propagation times for the communication of a larger number of cells in the same
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`direction, that is, along the same bus structure, via an appropriate combination of short and
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`long segments, even if buffer registers are provided. The bus structure in this context is
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`comparable to a street that has fast lanes and crawler lanes and enables a lane change at
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`predetermined intermediate positions.
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`In yet another example embodiment, the bus system may include a multiplicity of parallel
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`segment lines in which several parallel segment lines are provided with longer segments. The
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`longer segments of the segment lines that have longer segments do not all need to be of the
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`same length; a staggered arrangement may be provided.
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`When there is a greater number of parallel segment lines, the segment line ends and/or
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`interline elements may be disposed within the segment lines at an offset in relation to each
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`other in the bus direction. Typically, interline elements, such as, switches, registers,
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`multiplexers and drivers are provided at the segment line ends or leads. The hardware
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`technology implementation of these elements then requires substantial space, which may be
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`NYO 223655 8vl
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`INTEL - 1004
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`considerable compared to that of the lines to be disposed in the intermediate layers. The
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`offset disposition of these elements then ensures that space has to be provided only for
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`interline element arrays of, for example, two or three segment lines, but not for interline
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`element dispositions of all available segment lines. Also it is possible not to provide drivers
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`or registers for all interline element dispositions, but only to provide them every nth segment
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`end. However, in this case, it is advantageous that at least three segment lines that have
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`longer segments for at least two segment lines have segment line switching circuits, in
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`particular multiplexers provided at predetermined positions as interline elements. In this way,
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`the desired segment change may be configured as required. Segment changes occur at
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`crossings and are possible among segment pairs or segment groups that vary along the bus. It
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`is then possible that the segment line switching circuits for the change from a first to a second
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`segment line are provided at a first position and the segment line switching circuits for the
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`switch from a second to a third segment line at a second position.
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`In addition to switching by pairs, it is also possible to select, at a position or a multiplicity of
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`positions, among several segment lines to switch to and/or to which data are simultaneously
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`output.
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`In an additional aspect of the present invention, two—way communication of the cells is
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`possible for the logic cell array. In bus systems having interline elements, such as drivers
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`and/or registers, directions of travel are defined. In order to enable the communication of the
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`cells in two directions, separate bus systems are provided for opposite running directions. At
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`least in one direction, it is once again possible to provide at least two different segment lines
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`with shorter and longer segments, in particular ones that are once again generally parallel.
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`If the segment lines are separate for the two directions of travel, a register may be provided
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`for at least one direction of travel. As explained above, the register may be provided in the
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`bus system that is routed in the reverse direction, i.e., to that bus system, with which signals
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`may be routed back from an element output to an element input.
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`According to another aspect of the present invention, a first bus system may be provided for
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`the transmission of data to be processed and a second bus system may be provided for the
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`transmission of status and]or monitoring or control information. One or both bus systems
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`may be formed with segment lines having short and long segments, and the resPective bus
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`systems or bus arrays may be configurable separately fiom each other, or definable in their
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`circuitry and/or regarding the operations in linking registers or the output of lookup tables.
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`The bus system may be used in a logic cell array in which a plurality of logic cells are
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`arranged adjacent to each other in a row. The longer segments then bypass at least one logic
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`NYO 2236558v1
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`6
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`INTEL - 1004
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`Page 8 of 362
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`INTEL - 1004
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`cell. If the logic cell array includes even more logic cells in a row, the longest segments may
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`bypass more than one logic cell.
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`It should be pointed out that, in at least two-dimensional logic fields having a disposition of
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`logic cells in rows and columns, a segmented bus system may be provided in each row and
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`each column and have the previously described structure having long and short segments in
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`parallel segment lines.
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`The described bus structure may be advantageous in arrays in which data processing units,
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`such as logic units, are to be linked to each other. However, special advantages are offered if
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`the logic cells are selected fi'om, include and/or form arithmetic-logic units, DPGA's, Kress
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`arrays, systolic processors and RAW machines, digital signal processors (DSP’s) that have
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`more than one arithmetic—logic unit, configurable (programmable) logic cells or other cores
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`and/or PAE's, ALU, input/output (I/O) functions and/or memory management units (I/O) and
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`memories. A successful implementation of a bus structure having segment lines that have
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`short and long segments is the VPU / XPP processor unit produced by the applicant.
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`Such a processor may have a multiplicity of different communicating logic units disposed in
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`an array, the logic units having at least memory storage and data conversion units and the
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`memory units being disposed close to the edge of the array. This makes it possible to have
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`data run through the array and be buffered, if necessary, at the edge in order to bring about
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`reconfiguration as required. The flow may also occur via parallel rows or columns and/or in a
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`meandering way, in order to thereby provide increased computing power.
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`Additionally, input/output units may be disposed closer to the edge than the storage units.
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`This allows the buffering of data before processing by passing through the array. However, in
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`any case communication of the logic units, at least fiom edge to edge, for at least one bus
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`system to be provided that is, in particular, segmentable as previously described. Then, data
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`read from a first memory that is close to the edge may be changed as required in a first data
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`conversion unit that is close to this edge, and transferred from there into at least one other
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`data conversion unit in order to carry out further data modifications as required. The data,
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`afler flowing through a plurality of data conversion units into a second memory close to the
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`edge may be stored at a position distant from the first memory, and then a reconfiguration of
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`the data conversion units may be carried out for the re—determination of the data conversion,
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`and the data may be routed through at least one part of the data conversion units, possibly in
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`the opposite direction of travel. It may also be provided that the outgoing run is made in a
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`row and the return run in that row or a row situated beneath it in order to take into
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`consideration pipeline effects.
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`NYO 2236553v1
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`7
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`INTEL - 1004
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`Page 9 of 362
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`INTEL - 1004
`Page 9 of 362
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`The processor may have at least one programmable gate array (PGA) and several data
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`modification units having ALU‘s. At least one PGA may be surrounded by other data
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`conversion units, in particular ALU's, in order to be able to obtain data easily for linking
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`purposes and/or output them.
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`It is possible that, in an array made up of reconfigurable units, several (sub—) arrays,
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`particularly identical ones, are provided that may