PINAKI MAZUMDER1
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`Room Number: 4765, Computer Science and Engineering Building, Department of Electrical Engineering and
`Computer Science, 2260 Hayward Avenue, University of Michigan, Ann Arbor, MI 48109-2121.
`Phone: 734-763-2107 (Office), and Fax: 734-763-8094. E-Mail: mazum@eecs.umich.edu
`
`Please see Mazumder’s homepage at http://www.eecs.umich.edu/~mazum
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`Immigration Status: US Citizen (1995); Permanent Resident (1989-1995).
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`I. Educational Qualification
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`Ph.D. in Computer Engineering
`M. Sc. in Computer Science
`B.S. in Electrical Engineering
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`University of Illinois, Urbana-Champaign
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`University of Alberta, Edmonton, Canada
`Indian Institute of Science, Bangalore, India
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`1988
`1985
`1976
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` I
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` also received a degree in B.Sc. Physics Honors securing the first rank in Guwahati University, India amongst
`estimated 100,000 students in all disciplines of liberal arts and basic sciences.
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`II. Work Experience
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`US Government (National Science Foundation):
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`2007-2008
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`Program Director for Emerging Models and Technologies Program (funding areas:
`Nanoelectronics, Quantum Computing, and Biologically Inspired Computing with an annual
`budget of $18 Million) in the Directorate for Computer and Information and Science and
`Engineering, National Science Foundation, Arlington, Virginia.
`
`Program Director in Electrical, Communications and Cyber Systems Division (funding areas:
`Quantum, Molecular and High Performance Computing, Adaptive Intelligent Systems,
`Electronic and Photonic Devices, and Major Research Instrumentation) of the Engineering
`Directorate at National Science Foundation.
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`2009
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`1996-1997
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`1996-1997
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`1997
`1992-1998
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`1987-1992
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`Academic Teaching and Research:
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`1998- to date
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`Tenured Professor, Division of Computer Science and Engineering, Department of Electrical
`Engineering and Computer Science, University of Michigan, Ann Arbor, USA.
`Research Fellow, Division of Electrical and Computer Engineering, Department of Electrical
`Engineering and Computer Science, University of California, Berkeley, USA.
`Visiting Associate Professor, Department of Computer Science and Engineering, Stanford
`University, Palo Alto, California, USA.
`Visiting Professor, NTT Basic Research Laboratories, Atsugi-shi, Japan.
`Tenured Associate Professor, Division of Computer Science and Engineering,
`Department of Electrical Engineering and Computer Science, University of Michigan,
`Ann Arbor, USA.
`Assistant Professor, Division of Computer Science and Engineering, Department of
`Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA.
`Research Assistant, University of Illinois at Urbana-Champaign, USA.
`Teaching Assistant at University of Alberta, Edmonton, Canada.
`Research Assistant at Indian Institute of Science, Bangalore, India.
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`
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`1985-1987
`1982-1984
`1974-1975
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`1 Fellow of AAAS, Fellow of IEEE, Member of Sigma Xi, and Member of Phi Kappa Phi
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`Member of Technical Staff, AT&T Bell Laboratories, Indian Hill, Chicago
`Senior R&D Engineer, Bharat Electronics Ltd., Bangalore, India
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`Industrial Research and Development:
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`1985, 1986
`1976-1982
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`III. Major Fields of Research
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`1) VLSI design, testing and layout automation; 2) Nanoelectronics and nanomagnetics: multiscale modeling,
`simulation tools, circuits and architectures; 3) Terahertz technology and applications in signal processing,
`computing and communications.
`
`IV. Awards and Recognitions
`
`
`• Fellow of American Association for the Advancement in Science (AAAS), 2007 for “distinguished
`contributions to the field of very large scale integrated (VLSI) systems”. The honor of being elected a
`Fellow of AAAS is given to those whose “efforts on behalf of the advancement of science or its
`applications are scientifically or socially distinguished.”
`• Fellow of IEEE, 1999 for “contributions to the field of VLSI Design.”
`•
`IEEE Distinguished Lecturer
`• Digital Equipment Corporation Faculty Award: Excellence in Research
`• Departmental Research Excellence Award (1995), The University of Michigan
`• BF Goodrich National Collegiate Invention Award
`• DARPA Research Excellence Award for the work in Quantum MOS Project
`• Best Undergraduate Student Medal
`•
`IETE Best Student Paper Award, and IETE Best Paper Presentation Award
`• NSF Research Initiation Award
`• Bell Northern Research Laboratory Faculty Development Grant
`• Commendation Letter from the Dean of College of Engineering, University of Michigan, for Excellence in
`Teaching
`• Member, Sigma Xi
`• Member, Phi Kappa Phi
`
`
`V. Research Funding
`
`
`1. National Science Foundation (RIA): $69,948; 1988 – 1991 (Single PI)
`2. Bell Northern Research Laboratory: $20,900; 1988 – 1989 (Single PI)
`3. National Science Foundation: $90,620; 1989 – 1990 (Single PI)
`4. Digital Equipment Corporation: $180,000; 1989 – 1992 (Single PI)
`5. Office of Naval Research: $420,000; 1988 - 1991, (Co-PI)
`6. National Science Foundation: $125,000; 1991 – 1993 (Single PI)
`7. Rackham Faculty Research Grant: $9,980; 1991 – 1993 (Single PI)
`8. U.R.I. Program (US Army): $6,000,000 (total); $250,000 (my portion); 1988 - 1992
`9. General Motors: $20,000; 1992 – 1992 (Single PI)
`10. International Business Machines: $45,000 (student fellowship); 1990 – 1993
`11. National Science Foundation: $47,000; 1992 – 1993 (Single PI)
`12. Hewlett Packard: $81,400; 1993 – 1995 (Single PI)
`13. Office of Vice President Research: $52,300; 1995 - 1996
`14. Defense Advanced Research Projects Agency (DARPA): $825,000; 1993 -1997 (Co-PI)
`15. National Science Foundation: $182,400; 1994 – 1998 (Single PI)
`16. U.R.I. Program (US Army): $5,000,000; $200,000; 1993 - 1997
`17. State of Michigan Display Technology Center: $2,000,000; My portion: $200,000; 1995 - 1998
`18. Texas Instruments (subcontract of a DARPA project): $304,000; 1995 – 1998 (Single PI)
`19. Army Research Office’s MURI-95 (Co-PI with 7 others): $4,000,000; 1995-2000 + 1 year.
`20. Army Research Office’s MURI-96 (Co-PI with 13 others): $5,000,000; 1996-2001 + 1 year.
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`21. Defense Advanced Research Projects Agency: $750,000; June 1997- May 2000 (PI)
`22. National Science Foundation: $300,000; 1998 – 2002 (Single PI)
`23. Nippon Electric Company, Japan: $40,000; 1998 (Single PI)
`24. National Science Foundation: $195,000; 1998 – 2002 (Single PI)
`25. Office of Naval Research; $270,000; 1998-2001 (Single PI)
`26. NanoLogic Inc. $10,000; 1999-2000 (Single PI)
`27. Air Force Office of Scientific Research: $5,000,000: 2001-2006 (Co-PI with 9 other investigators)
`28. Office of Naval Research: $303,000: 2001-2002; (Single PI)
`29. National Science Foundation: $210,000: 2001-2004 (Single PI)
`30. Korean Government Nanoelectronics Research: $200,000: 2001-2002 (PI: Prof. G.I. Haddad).
`31. Office of Naval Research: $820,000: 2002-2005 (PI)
`32. Tera-Level Nanoelectronics Project, Korean Government: $170,000: 2003-2006; (Single PI)
`33. National Science Foundation: $120,000: 2004-2007 (Single PI)
`34. Air Force Office of Scientific Research, $480,000: 2006-2009 (Single PI)
`35. National Science Foundation IPA Assignment Grant: $620,000; 2007-2009 (Single PI)
`36. DARPA SyNAPSE Program on Brain Plasticity: $807,812; Co-PI: Hughes Research Laboratory
`37. National Science Foundation, NIRT: $1,000,000: 2006-2012 (Co-PI).
`38. SRC NRI Center (MIND): ~$200,000: 2008-2011 (Single PI)
`39. National Science Foundation: EAGER Grant, $200,000; 2009-2012. (Single PI)
`40. National Science Foundation: $400,281; 2010-2014. (Single PI)
`41. Army Research Office: $580,000; 2010-2013. (Single PI)
`42. National Science Foundation: $149,111; 2011-2012. (Single PI)
`43. Army Research Office, MURI: $6,500,000; 2010-2015. (Co-PI)
`44. National Science Foundation: $400,415; 2011-2014. (Single PI)
`45. National Science Foundation: $1,750,000; 2011-2015. (Co-PI)
`46. Defense Advanced Research Projects Agency (DARPA): $150,000; 2011-2013 (Single PI)
`47. Air Force Office of Scientific Research: $449,772; 2012-2015 (Single PI)
`48. National Science Foundation: $480,000; 2012-2015 (Co-PI)
`49. National Science Foundation: $400,000; 2014-2017 (PI)
`50. National Science Foundation: $900,000; 2015-2018 (PI).
`51. Air Force Office of Scientific Research: $150,000; 2016-2017 (Single PI)
`52. National Science Foundation: $330,000; 2017-2020 (Single PI)
`53. National Science Foundation: $620,000; 2017-2020 (PI)
`54. Air Force Office of Scientific Research: $501,000; 2018-2021 (Single PI)
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`Pending Proposals:
`
`1. Engineering Research Center (ERC): Foundation for Integrative Research on Short-range Terahertz in
`Wireless Communication and Signal Processing, National Science Foundation, $18,000,000 for 5 years
`(Mazumder, PI; University of Michigan, Massachusetts Institute of Technology, University of California at
`Los Angeles, New Jersey Institute of Technology, University of Central Florida, and Cornell University).
`2. Nanoarchitectures for Adaptive Control and Intelligence Processing Chips, Office of Naval Research,
`$450,000 (PI)
`3. Ultra-Low-Power Bio-inspired Nanoelectronics for Navigation in Autonomous Insect-Scale Robots, Air
`Force Office of Scientific Research, $790,000 (PI)
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`VI. Committees and Professional Activities
`
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`1. Nomination Committee Member for The Blue Planet Prize, an international environmental award
`sponsored awarded by Asahi Glass Foundation, Japan, 2015-
`2. Member of Board of Editors, Proceedings of the IEEE, 1999-2002
`3. Associate Editor, IEEE Transactions on VLSI Systems, 1997-2000
`4. Guest Editor, IEEE Transactions on VLSI Systems - A Special Issue on Impact of Emerging Technologies
`on VLSI Systems, December 1997
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`5. Guest Editor (with Prof. A. Seabaugh), Proceedings of the IEEE - A Special Issue on Nanoelectronic
`Devices and Circuits, June 1998.
`6. Guest Editor (with Prof. S. M. Kand and Prof. R. Wasser), Proceedings of the IEEE - A Special Issue on
`Memristors: Device, Models, and Applications, June 2012.
`7. Guest Editor (with Prof. A. Benso and Prof. Y. Makris), IEEE Transaction on Computer – A Special Issue
`on Architectures for Emerging Technologies and Applications, June 2008
`8. Guest Editor, Journal of Electronic Testing - Theory and Application - A Special Issue on Multi-megabit
`Memory Testing, April 1994
`9. Guest Editor (with Prof. J.P. Hayes), IEEE Design & Test Magazine - A Special Issue on Memory Testing,
`1993
`10. Editorial Advisory Board, The Arabian Journal for Science and Engineering, King Fahd University of
`Petroleum and Minerals, Saudi Arabia.
`11. Council of Editors, International Society for Genetic and Evolutionary Computation (ISGEC)
`12. As lead NSF Program Director, organized the Emerging Models and Technology Workshop on Bio-
`Inspired Computing and Bio-Computing at Princeton University on July 24-25, 2008.
`13. As lead NSF Program Director, organized the EMT Workshop on Nanoelectronics on October 29-30, 2007.
`14. As lead NSF Program Director, held the EMT Workshop on Quantum Information Science and
`Engineering on September 10-11, 2007.
`15. Member, University of Michigan Research Policies Committee of Senate Assembly, 2002-05.
`16. Member, Electrical Engineering and Computer Science Curriculum Committee, 2002-03.
`17. Member, Electrical Engineering and Computer Science DCO Committee, 2002-03.
`18. Member, Computer Science and Engineering Graduate Curriculum Committee, 1988-89, 1998-00, 2002-06.
`19. Counselor, Computer Engineering Undergraduate Students, 1990-95.
`20. Member, Computer Science and Engineering Graduate Admission Committee, 1995-96.
`21. Member, IEEE Standards Subcommittee for Semiconductor Memories, 1989-90.
`22. Member, IEEE Test Technologies Committee
`23. Member, IEEE VLSI Technical Committee
`24. General Chair, 2007 High Performance Computing (HPC) for Nanotechnology
`25. General Chair, 1999 IEEE Great Lakes VLSI Conference
`26. Program Committee, 1992 Fault-Tolerant Computing Symposium Workshop
`27. Program Committee, 1992 IEEE Defects and Fault Tolerance Workshop
`28. Program Committee, 1993 IEEE Intl. Conference on Memory Testing
`29. Program Committee, 1994 IEEE Intl. Conference on Memory Testing
`30. Program Committee, 1994 IEEE Asian Testing Symposium
`31. Program Committee, 2000 IEEE Great Lakes VLSI Conference
`32. Serving on organizing committee for Department of Defense Nano Conference, 2009
`33. Served regularly on NSF panels in Engineering and CISE Directorates
`34. Proposals Reviewed for: US National Science Foundation, The Israel Science Foundation, Louisiana
`University Board of Regents, and US Army Research Office, New Jersey Center for Science and
`Technology, Saudi Arabia King Fahd University Research Foundation, and private venture capitalist firms.
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`VII. Professional Experience
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`Details of My Professional Accomplishments
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`US Government at National Science Foundation (3 years)
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`In 2007 and 2008, I worked as the lead Program Director for Emerging Models and Technologies (EMT)
`program in the Division of Computing and Communication Foundations (having nearly $140 Million annual budget)
`of the Directorate for Computer and Information and Science and Engineering, National Science Foundation,
`Arlington, Virginia. My mandate was to manage research grants in Nanoelectronic Modeling and Systems,
`Quantum Computing, and Biologically Inspired Computing for which I had an operating annual budget of about $18
`Million. Additionally, I participated in several NSF crosscutting programs such as Cyber-Enabled Discovery and
`Innovation (CDI), Expeditions in Computing, Major Research Instrumentation (MRI), Computing Research
`Infrastructure (CRI) and Cyber Physical Systems (CPS). In 2009, I worked as a Program Director in the Engineering
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`Directorate where I managed research in three broad areas: Adaptive Intelligent Systems (Machine Learning),
`Quantum, Molecular and High-Performance Modeling, and Electronic and Photonic Devices. During these three
`years, I interacted with several program managers and administrators of NSF, DARPA, ARO, ONR, and AFOSR to
`help launch national-level major research initiatives. I consider that serving the US government for a stint of three
`years has provided me an exceptional opportunity to acquire a vast amount of knowledge in various fields of science
`and engineering, to network with numerous researchers around the nation, and to gain divergent administrative
`experience.
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`Teaching Experience (29 years)
`
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`Since 1988, I have been teaching at the Department of Electrical Engineering and Computer Science of the
`University of Michigan, Ann Arbor, Michigan.
`
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`Graduate courses developed and taught: 1) VLSI System Design, 2) Optimization and Synthesis of VLSI
`Layout, 3) Testing of Digital Circuits and Systems, 4) Advanced Computer Architectures, 5) Nanocircuits and
`Nanoarchitectures, 6) Ultra-Low-Power Subthreshold CMOS Circuits, and 7) Terahertz Technology and
`Applications.
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`Undergraduate courses upgraded and taught: 1) Introduction to Digital Logic Design (sophomore level), 2)
`Digital Integrated Circuit Design (junior level), and 3) VLSI System Design (senior level).
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`Industrial Experience (6.5 years)
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`After my baccalaureate degrees in Physics and Electrical Engineering, I worked for six years (1976-1982)
`as a Senior R&D Engineer at Bharat Electronics Ltd. (BEL) in its Integrated Circuits Division. I designed several
`bipolar and CMOS analog and digital integrated circuits for consumer electronic systems. I was associated with the
`following chip development projects: i) Raster-scan vertical deflection system microchip for TV display, ii) Sync
`processing and horizontal deflection system microchip for TV display, iii) Video and audio IF stage IC’s for
`vestigial-AM and FM signal detection in TV receiver, iv) High-gain audio amplifier microchip for TV audio stage,
`v) Tape Recorder IC with automatic gain adjustments, vi) Hearing-aid IC, vii) Analog clock driver IC, and viii)
`LCD and AC Plasma display drive IC’s. Several million commercial chips were fabricated based on these designs.
`
`After finishing my MSc degree in Computer Science and while working towards my PhD degree in
`Electrical and Computer Engineering, I worked during the summers of 1985 and 1986 as a Member of Technical
`Staff at AT&T Bell Laboratories. I was one of the two engineers who started the Bell Laboratory Cones/Spruce
`project - a new behavioral synthesis and layout automation tool for rapid prototyping of digital circuits. The main
`contribution of this effort was to demonstrate how a restricted version of C language could be used to model digital
`hardware much before commercial hardware description language (HDL) software tools like Verilog and System C
`were designed.
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`Teaching Accomplishments and Evaluations:
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`I have endeavored to pursue multidimensional education frontiers that transcend the confines of classroom
`and impact students as well as other professionals alike. My teaching contributions include authoring an
`undergraduate textbook and a video book, developing four advanced graduate courses, developing courseware for
`practicing engineers in industry, editing special issues in professional journals to stimulate research in emerging
`technologies, and fostering STEM education for K-12 students. Highlights of my teaching accomplishments are
`enumerated below:
`
`• Breakdown of my course offering at the University of Michigan over the past 30 years: (i) nearly 60% of courses
`I taught are on three undergraduate courses for sophomore, junior and senior; approximately 10% of
`courses are on two regular graduate courses; and about 30% of courses are on four new graduate courses
`designed and developed by me to promote the state-of-the-art CMOS research and train the future
`engineering workforce. I have taught three distinct undergraduate and six graduate courses at the University
`of Michigan.
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`• Authored an undergraduate textbook, “Lectures on Digital Logic Design”, about 500 pages. This book is based on
`my lectures in an introductory Digital Logic Design (EECS 270) course that I taught nearly twenty times at
`the University of Michigan.
`
`• Developed an “on-line course” on Digital Logic Design (NEEP 2221), which was produced in June 2005 at the
`Disney MGM Studio, Orlando, Florida by National Technological University (NTU), now acquired by
`Walden University that is widely regarded as a global leader in on-line education. With the support of
`major technology companies such as IBM, Motorola, and Hewlett-Packard, the NTU was founded in 1984
`to deliver academic courses to training facilities of corporations via a unique satellite network.
`
`• Developed a new graduate course on Ultra-Low-Power Sub-threshold CMOS Design (EECS 598-1):
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`• Developed a new graduate course on Nanocircuits and Nanoarchitectures (EECS 598-2):
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`• Developed a new graduate course on Terahertz Engineering: Theory and Applications (EECS 598-6) to promote
`research in spoof plasmonics, photonics, and microwave electronics.
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`• Developed a new graduate course on Optimization and Synthesis of VLSI Layout (EECS 527) that I taught nearly
`half-a-dozen times. When I taught the course for the first time in 1988, there was no suitable textbook at
`that time. Therefore, I developed course materials, which were also adopted in other universities to teach
`new VLSI computer-aided design (CAD) course at that time.
`
`• Co-authored six advanced VLSI books to promote education in VLSI chip design and semiconductor memory
`technology. Our book on “Genetic Algorithms for VLSI Design, Layout and Testing”, Prentice Hall, 2000
`provides the foundation for developing distributed VLSI design automation tools by exploiting the
`multidimensional optimization capability of GA’s running concurrently on a network of workstations to
`rapidly solve problems. The book not merely brings the evolutionary computing and the broader
`engineering community together enabling them to solve complex engineering problems. The book also
`unravels many mathematical insights for constructing multidimensional chromosome operators, and
`challenges mathematicians to develop theoretical models for the evolutionary algorithms. Two of books I
`coauthored on semiconductor memory systems are “Testing and Testable Design of Random-Access
`Memory”, Kluwer Academic Publisher, 1996; and “Fault Tolerance and Reliability Aspects of Random-
`Access Memories,” Prentice Hall, 2002. They are being widely used by practicing engineers and
`researchers in semiconductor memory technologies because of their pedagogical values. The names of
`other books are listed in Publications section.
`
`• Edited a Special Issue in The Proceedings of the IEEE on Memristors: Devices, Models and Circuits, which can
`be adapted for teaching the next generation nano-circuits and nano-architectures.
`
`• To promote STEM education among K-12 students through imaginative mathematics software, I started
`developing Math Guru with the help of one of my ex advisees. The software was demonstrated in 1996-97
`at local schools and distributed. http://web.eecs.umich.edu/~mazum/mathguru.pdf.
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`Numerous studies conducted by professional societies such as American Society for Engineering Education
`
`
`(ASEE) and National Academy of Engineering (NAE) have ardently advocated for educator’s multidimensional
`impact, in addition to conventional measures such as numerical rating and student feedback that serve as a rough
`metric for classroom performance. My numerical scores for teaching in courses I taught are provided below. While
`these data reflect my deeper commitments for education and training, I continually strive to impart broader impact
`by pursuing multidimensional teaching activities and training the future engineering workforces through integration
`of research and teaching.
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`Teaching Rating
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`Q#1: This is an excellent teacher
`Q#2: This is an excellent course
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`EECS 427: VLSI Design
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`Winter 2018 Evaluation: 4.88/5.0 (Q#1:excellent teacher) and 4.88/5.0 (Q#2:excellent course);
`Winter 2016 Evaluation: 4.71/5.0 (Q#1) and 4.58/5.0 (Q#2);
`Winter 2015 Evaluation: 4.71/5.0 (Q#1) and 4.55/5.0 (Q#2);
`Winter 2014 Evaluation: 4.58/5.0 (Q#1) and 4.42/5.0 (Q#2)
`Winter 2013 Evaluation: 4.2/5.0 (Q#1) and 4.33/5.0 (Q#2)
`Fall 1997 Evaluation: 4.71/5.0 (Q#1) and 4.58/5.0 (Q#2
`Fall 1995 Evaluation: 4.55/5.0 (Q#1) and 3.94/5.0 (Q#2)
`Fall 1994 Evaluation: 4.81/5.0 (Q#1) and 4.12/5.0 (Q#2)
`Fall 1993 Evaluation: 4.32/5.0 (Q#1) and 3.83/5.0 (Q#2)
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`EECS 527: Computer-Aided Design for VLSI Systems
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`Winter 1988 Evaluation: 3.83/5.0 (Q#1) and 4.00/5.0 (Q#2)
`Fall 1989 Evaluation: 4.81/5.0 (Q#1) and 4.67/5.0 (Q#2)
`Winter 1992 Evaluation: 4.00/5.0 (Q#1) and 4.25/5.0 (Q#2)
`Winter 1995 Evaluation: 4.25/5.0 (Q#1) and 4.08/5.0 (Q#2)
`Winter 1996 Evaluation: 4.50/5.0 (Q#1) and 4.10/5.0 (Q#2)
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`EECS 598: Ultra-Low-Power CMOS System Design
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`Fall 2012: Evaluation: 4.0/5.0 (Q#1) and 4.17/5.0 (Q#2)
`Fall 2013 Evaluation: 4.5/5.0 (Q#1) and 4.5/5.0 (Q#2)
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`EECS 570: Advanced Computer Architecture
`Winter 1989: Evaluation: 4.08/5.0 (Q#1) and 3.67/5.0 (Q#2)
`Winter 1991: Evaluation: 4.20/5.0 (Q#1) and 3.89/5.0 (Q#2)
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`EECS 270: Digital Logic Design (Regular term class size is frequently above 100 students)
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`Winter 1988: Evaluation: 3.84/5.0 (Q#1) and 3.45/5.0 (Q#2)
`Fall 1990: Evaluation: 4.41/5.0 (Q#1) and 3.80/5.0 (Q#2)
`Spring 1991: Evaluation: 4.54/5.0 (Q#1) and 4.71/5.0 (Q#2)
`Spring 1992: Evaluation: 4.6/5.0 (Q#1) and 4.43/5.0 (Q#2)
`Spring 1993: Evaluation: 4.24/5.0 (Q#1) and 4.59/5.0 (Q#2)
`Winter 1998: Evaluation: 3.76/5.0 (Q#1) and 3.41/5.0 (Q#2)
`Winter 2001: Evaluation: 4.02/5.0 (Q#1) and 4.32/5.0 (Q#2)
`Fall 2011: Evaluation: 4.17/5.0 (Q#1) and 3.75/5.0 (Q#2)
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`Legend: 5.0 – Excellent, 4.0 – Very Good, 3.0 – Good, 2.0 – Fair, 1.0 – Poor.
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`Research Accomplishments:
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`In 1984, when I started my MS thesis at University of Alberta in the field of VLSI, I was inspired by the
`local (Edmonton, Canada) hockey legend, Wayne Gretzky whose famous quote (“A good hockey player plays where
`the puck is. A great hockey player plays where the puck is going to be”) defined the compass of my research work
`for the next 28 years as explained below. In Evolutionary CMOS research, I solved numerous use-inspired research
`problems that were 10 to15 years ahead of their time and eventually Moore’s Law has vindicated the practical merits
`of my research by impacting the memory and FPGA industry as pointed out below. In Revolutionary emerging
`technologies such as quantum tunneling devices, THz plasmonic devices (in THz regime), ionic devices (as non-
`volatile memories), and electron spin based devices (as ultra-low-power nonvolatile memories) I have made
`sustained impact for the past 23 years by collaborating with multiple leading researchers in universities and
`companies. In my research career, I have endeavored to emulate the Vannevar Bush model of triad synergy between
`University, Industry and Government establishments that was conceived at the aftermath of the Second World War
`to challenge academics to undertake enterprising and leadership role for catalyzing innovations, accelerated
`economic growth, and sustained US leadership in science and engineering.
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` Details of my Research Accomplishments are provided at pp. 47-48 of this CV.
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`VIII. Publications
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`Summary of Significant Publications
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`Books: 13; Journal Publications: 123; Reviewed Conference Papers: 191; Book Chapters: 6; US Patents
`Granted: 10; US Patents under Review: 3.
`
`A. Books
`
`
`1. P. Mazumder and K. Chakraborty, “Testing and Testable Design of Random-Access Memories”, Kluwer
`Academic Publishers, 1996 (428 pages).
`
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`2. P. Mazumder and E. Rudnick, “Genetic Algorithms for VLSI Layout and Test Automation”, Prentice Hall,
`1999 (460 pages).
`
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`3. K. Chakraborty and P. Mazumder, ”Fault Tolerance and Reliability Aspects of Random-Access Memories,”
`Prentice Hall, 2002. (440 pages).
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`4. V. Ramachandran and P. Mazumder, “Handbook for VLSI Routing – Serial and Parallel Models”, Tsinghua
`University Publisher, 2018 (340 pages).
`
`5. P. Mazumder and I. Ebong, “Lectures on Digital Logic Design”, Pan Stanford Publishing, 2018 (550 pages).
`
`6. N. Zheng and P. Mazumder, “Learning in Energy-Efficient Neuromorphic Computing: Algorithm and
`Architecture Co-Design”, John Wiley and Sons, 2018 (275 pages).
`
`Books under Preparation
`
`
`7. P. Mazumder, Y. Yalcin, I. Ebong, and W.H. Lee, “Neuromorphic Circuits for Nanoscale Devices,” Springer
`Verlag, 2018 (300 pages).
`
`8. P. Mazumder. K. Song, X. Zhao and M. Aghdajani, “Terahertz Spoof Plasmonics: Theory and Applications,”
`(Publisher to be decided).
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`9. P. Mazumder, S. Kulkarni, A. Gonzalez, S. Mohan, and M. Bhattcharya, “Quantum Electronic Devices:
`Modeling and Circuits,” (Publisher to be decided).
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`Edited Books & Other Categories
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`10. R. Rajasuman (Editor) and P. Mazumder (Editor), “Semiconductor Memories: Testing and Reliability”,
`Computer Science Press, May 1998.
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`11. R. J. Lomax (Editor) and P. Mazumder (Editor), “Great Lakes Symposium on VLSI, 1999”, Computer
`Science Press, March 1999.
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`12. P. Mazumder, “Introduction to Digital Systems”, Video Book on DVD, produced at MGM Studio (Orlando,
`Florida), Laureate Education, Inc., 2005.
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`13. P. Mazumder and K. Shahookar, “MathGuru Tutorial” for K-12 Education Software.
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`B. Reviewed Journal Publications
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`SEMICONDUCTOR MEMORIES
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`Dynamic Random Access Memory (DRAM)
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`14. P. Mazumder, J. H. Patel and W. K. Fuchs, “Methodologies for Testing Embedded Content-Addressable
`Memories”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, No.
`1, Jan. 1988, pp. 11-20.
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`15. P. Mazumder, “Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-Access
`Memory”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp. 933-942.
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`16. P. Mazumder and J. H. Patel, “Parallel Testing of Pattern-Sensitive Faults in Random-Access Memory”, IEEE
`Transactions on Computers, Vol. 38, No 3, Mar. 1989, pp. 394-404.
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`17. P. Mazumder and J. H. Patel, “An Efficient Built-In Self-Testing Algorithm for Random-Access Memory”,
`IEEE Transactions on Industrial Electronics (Special Issue on Testing) Vol. 36, No. 3, May 1989, pp. 394-
`407.
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`18. J. S. Yih and P. Mazumder, “Circuit Behavior Modeling and Compact Testing Performance Evaluation”,
`IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, Jan. 1991, pp. 62-65.
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`19. P. Mazumder and J. H. Patel, “A Comprehensive Study of Random Testing for Embedded RAM’s Using
`Markov Chains”, Journal of Electronic Testing: Theory and Applications, Vol. 3 No. 4, Nov. 1992, 235-250.
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`20. P. Mazumder and J. P. Hayes, “Testing and Improving the Testability of Multi-megabit Memories”, IEEE
`Design and Test of Computers, Vol. 10, Issue 1, Mar. 1993, pp. 6-7.
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`21. P. Mazumder, J. H. Patel and J. A. Abraham, “A Reconfigurable Parallel Signature Analyzer for Concurrent
`Error Correction in Dynamic Random-Access Memory”, IEEE Journal of Solid-State Circuits, Vol. 25, No.
`3, Jun. 1990, pp. 866-870.
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`22. P. Mazumder and J. Yih, “Restructuring of Square Processor Arrays by Built-in Self-Repair Circuit,” IEEE
`Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept. 1993, pp.
`1255-1265.
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`23. P. Mazumder, “A New On-Chip ECC Circuit for Correcting Soft Errors in DRAM’s with Trench Capacitors,”
`IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1623-1633.
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`24. R. Venkateswaran, P. Mazumder and K. G. Shin, “On Restructuring of Hexagonal Arrays,” IEEE
`Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 12, Dec. 1992, pp.
`1574-1585.
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`25. P. Mazumder, “Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-
`Chip Error-Correcting Circuit,” IEEE Transactions on Computers, Vol. 42, No. 12, Dec. 1993, pp. 1453-
`1468.
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`26. H. Zhang, P. Mazumder, L. Ding, and K. Yang, “Performance Modeling of Resonant Tunneling Random-
`Access Memories,” IEEE Transactions on Nanotechnology, July 2005, pp. 472-480.
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`Static Random Access Memory (SRAM)
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`27. K. Chakraborty and P. Mazumder, “New March Tests for Multi-port RAM Devices,” JETTA: Journal on
`Electronic Testing: Theory and Applications, Vol. 16, No. 4, Aug. 2000, pp. 389-396.
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`28. S. Mohan and P. Mazumder, “Analytical and Simulation Studies of Failure Modes in SRAM’s Using High-
`Electron Mobility Transistors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and
`Systems, Vol. 12, No. 12, Dec. 1993, pp. 1885-1896.
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`29. K. Chakraborty and P. Mazumder, “Technology and Layout Related Testing in Static Random-Access
`Memories”, Journal of Electronic Testing: Theory and Applications, Vol. 5, Issue 4, Aug. 1994, pp. 347-365.
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`30. K. Chakrabaorty, M. Bhattacharya, S. Kulkarni, A. Gupta and P. Mazumder, “BISRAMGEN: A Built-In
`Self-Repairable SRAM and DRAM Compiler,” IEEE Transactions on VLSI Systems, Vol. 9, No. 2, Apr.
`2001, pp. 352-364.
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`31.
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`J. Kim and P. Mazumder, “A Robust 12T SRAM Cell with Improved Write Margin for Ultra-Low
`Power Applications in 40 nm CMOS”, Integration, the VLSI Journal, Vol. 57, pp 1-10, March 2017.
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`32.
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`N. Zheng and P. Mazumder, “Modeling and Mitigation of Static Noise Margin Variation in Subthreshold
`SRAM Cells”, “IEEE Transactions on Circuits and Systems” to appear in 2017
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`Nonvolatile Semiconductor Memory (NVSM)
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`33. M. Barangi and P. Mazumder, “Straintronics-based Random-Access Memory as Universal Data Storage
`Devices,” IEEE Transactions on Magnetics, Vo. 51, No. 5, May 2015.
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`34. Y. Yilmaz and P. Mazumder, “Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain
`Nanomagnets,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.21, No.7,
`pp.1181-1188, July 2013.
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`35. M. Barangi and P. Mazumder, “Straintronics: A Leap Toward Ultimate Energy Efficiency of Magnetic
`Random-Access Memories”, IEEE Nanotechnology Magazine, Vol. 9, No. 3, Sept. 2015, pp. 15-24.
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`36. M. Barangi and P. Mazumder, “Straintronics-based True Random Number Generator for High-Speed and
`Energy-Limited Applicat