`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`
`INTEL CORPORATION,
`Petitioner
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner
`
`DECLARATION OF DR. PINAKI MAZUMDER UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 8,471,593
`
`INTEL - 1001
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`

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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`Page
`Introduction ...................................................................................................... 1
`Background and Qualifications ....................................................................... 3
`1.
`Educational Background ............................................................. 3
`2.
`Career Background ..................................................................... 5
`3.
`Relevant Publications .................................................................. 9
`4.
`Patents ....................................................................................... 13
`III. Understanding of Patent Law ........................................................................ 15
`IV. Background .................................................................................................... 18
`A.
`Background of the Field Relevant to the ’593 Patent ......................... 18
`1.
`Processors Generally ................................................................. 18
`2. Multiprocessor Systems ............................................................ 22
`3.
`Interconnects for Multiprocessor Systems ................................ 24
`Summary of the ’593 Patent ................................................................ 34
`1.
`The Alleged Problem in the Art ................................................ 34
`Summary of the Prosecution History .................................................. 36
`C.
`Level of Ordinary Skill in the Pertinent Art .................................................. 38
`V.
`VI. Background on Prior Art References ............................................................ 39
`A.
`Balmer ................................................................................................. 39
`B.
`Budzinski ............................................................................................. 41
`C.
`Gilbertson ............................................................................................ 45
`D. Hennessy ............................................................................................. 46
`
`B.
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`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`VII. Claims 1-2, 4-11, 14-17, 19-27 Are Obvious In View Of Balmer in
`combination with Hennessy ........................................................................... 48
`A.
`Challenged Claims .............................................................................. 48
`1.
`Independent Claims 1 and 16 .................................................... 48
`2.
`Dependent Claims 2 and 17 ...................................................... 71
`3.
`Dependent Claims 4 and 19 ...................................................... 72
`4.
`Dependent Claims 5 and 20 ...................................................... 76
`5.
`Dependent Claims 6 and 21 ...................................................... 79
`6.
`Dependent Claims 7 and 22 ...................................................... 83
`7.
`Dependent Claims 8 and 23 ...................................................... 83
`8.
`Dependent Claims 9 and 24 ...................................................... 87
`9.
`Dependent Claims 10 and 25 .................................................... 89
`10. Dependent Claims 11 and 26 .................................................... 91
`11. Dependent Claim 14 ................................................................. 92
`12. Dependent Claim 15 ................................................................. 95
`13. Dependent Claim 27 ................................................................. 97
`VIII. Claims 1-2, 4-11, 14-17, 19-27 Are Obvious In View Of Budzinski in
`combination with Hennessy ........................................................................... 99
`A.
`Challenged Claims .............................................................................. 99
`1.
`Independent Claims 1 and 16 .................................................... 99
`2.
`Dependent Claims 2 and 17 .................................................... 124
`3.
`Dependent Claims 4 and 19 .................................................... 128
`4.
`Dependent Claims 5 and 20 .................................................... 129
`5.
`Dependent Claims 6 and 21 .................................................... 131
`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`
`6.
`Dependent Claims 7 and 22 .................................................... 132
`Dependent Claims 8 and 23 .................................................... 133
`7.
`Dependent Claims 9 and 24 .................................................... 134
`8.
`Dependent Claims 10 and 25 .................................................. 136
`9.
`10. Dependent Claims 11 and 26 .................................................. 138
`11. Dependent Claim 14 ............................................................... 139
`12. Dependent Claim 15 ............................................................... 141
`13. Dependent Claim 27 ............................................................... 143
`IX. Claims 1-2, 4-11, 14-17, 19-27 Are Obvious In View Of Budzinski in
`combination with Gilbertson and Hennessy ................................................ 144
`A.
`Challenged Claims ............................................................................ 144
`1.
`Independent Claims 1 and 16 .................................................. 145
`2.
`Dependent Claims 2, 4-11, 14-15, 17, 19-27 .......................... 149
`Secondary Considerations of Non-Obviousness ......................................... 150
`X.
`XI. Conclusion ................................................................................................... 150
`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`I, Pinaki Mazumder, Ph.D., do hereby declare as follows:
`
`
`
`I.
`1.
`
`INTRODUCTION
`I have been retained as an expert witness on behalf of Intel Corporation (“Intel”)
`
`for the above-captioned Petition for Inter Partes Review (“IPR”) of U.S. Patent
`
`No. 8,471,593 (“’593 patent”). I am being compensated for my time in
`
`connection with this IPR at my standard consulting rate of $400 per hour. My
`
`compensation is not affected by the outcome of this matter.
`
`2.
`
`I have been asked to provide my opinions regarding whether claims 1-2, 4-11,
`
`14-17, and 19-27 of the ’593 patent (“the Challenged Claims”) are invalid as
`
`obvious to a person having ordinary skill in the art (“POSITA”) at the time of
`
`the alleged invention.
`
`3.
`
`In preparing my Declaration, I reviewed the ’593 patent, the file history of the
`
`patent, prior art references, technical references and other publications from the
`
`time of the alleged invention.
`
`4. The patent application that resulted in the ’593 Patent, Application No.
`
`13/289,296, was filed on November 4, 2011. Ex. 1003 (’593 Patent), Cover,
`
`Cert. of Correction. The ’593 patent claiming priority, through multiple
`
`divisional and continuation patents, to U.S. Patent Application No. 60/238,855,
`
`filed on October 6, 2000. Id.
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`
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`5. The named inventors of the ’593 Patent are Martin Vorbach, Frank May, Dirk
`
`Reichardt, Gerd Ehlers, Armin Nuckel, Volker Baumgarte, Prashant Rao, and
`
`Jens Oertel. Id. The original assignee of the ’593 Patent was PACT XPP
`
`TECHNOLOGIES AG. Id.
`
`6. For the purposes of my Declaration, I have been asked to assume that the
`
`priority date of the alleged invention recited in the ’593 Patent is October 6,
`
`2000.
`
`7.
`
`I understand that in Inter Partes Review (“IPR”) proceedings at the United
`
`States Patent and Trademark Office (“USPTO”), claims are given their ordinary
`
`and customary meaning in view of the patent specification and the
`
`understanding of one having ordinary skill in the relevant art.
`
`8.
`
`In forming the opinions expressed in this Declaration, I have relied upon my
`
`education and experience in the relevant field of the art and have considered the
`
`viewpoint of a POSITA as of the priority date of the ’593 patent. My opinions
`
`are based, at least in part, on the following references in view of the knowledge
`
`of a POSITA:
`
`Reference
`United States Patent No. 5,197,140
`(Ex. 1005, “Balmer”)
`
`Date of Public Availability
`Filed: November 17, 1989
`Issued: March 23, 1993
`prior art under §§ 102(a), (b), and
`(e)
`
`2
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`
`
`Reference
`European Patent Application
`0071727A1 (Ex. 1006),
`“Budzinski”)
`
`U.S. Patent No. 6,240,458 (Ex.
`1007, “Gilbertson”)
`
`John L. Hennessy & David A.
`Patterson, Computer Organization
`and Design: The
`Hardware/Software Interface (2d.
`ed. 1998) (“Hennessy”) (Ex. 1012)
`
`Date of Public Availability
`Filed: June 23, 1982
`Published: February 16, 1983
`prior art under §§ 102(a), (b), (e)
`
`Filed: Dec. 22, 1998
`Issued: May 29, 2001
`prior art under § 102(e)
`
`Published: 1998
`prior art under §§ 102(a), (b)
`
`
`II. BACKGROUND AND QUALIFICATIONS
`Educational Background
`1.
`I received my Bachelor of Science degree in Electrical Engineering from the
`
`9.
`
`Indian Institute of Science in Bangalore, India in 1976. I also received Bachelor
`
`of Science degree in Physics from Guwahati University in India in 1973, where
`
`I was the valedictorian across disciplines amongst approximately 100,000
`
`students.
`
`10. I received my Masters in Science degree in Computer Science from the
`
`University of Alberta in Edmonton, Canada in 1985. My M.S. thesis related to
`
`“Networks and Embedding Aspects of Hyper-cellular Structures for On-Chip
`
`Parallel Processing.” The thesis evaluated different types of multiprocessing
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`architectures by developing a new VLSI asymptotic modeling technique and
`
`demonstrated that meshes and torus class of interconnection topologies were
`
`most suited for on-chip parallel processing. The thesis also developed cellular
`
`layout techniques for placement and wiring of processors to embed fault-
`
`tolerant mesh networks. The core cellular embedding technique was extended
`
`to describe planar tessellation of quad-tree data-structures in computer vision,
`
`graphics and image processing.
`
`11. I continued on to receive my Ph.D. in Electrical and Computer Engineering
`
`from the University of Illinois in Urbana-Champaign, Illinois in 1988. My
`
`doctoral work focused on the semiconductor design of testable memory
`
`products, which were subsequently adopted and used in DRAM devices by
`
`several semiconductor manufactures in the industry. Since that time, I have
`
`secured 54 research grants amounting to nearly $54 million collectively from
`
`National Science Foundation, Air Force Office of Scientific Research, Office
`
`of Naval Research, Army Research Office, Defense Advanced Research
`
`Projects Agency, State of Michigan, and several private sources. These grants
`
`allowed me to perform research in areas including CMOS design tools, nano-
`
`circuit and nano-system design, testable designs for memories, and the use of
`
`ionic and/or spin-based devices as non-volatile memory.
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`12. I was a recipient of Digital’s Incentives for Excellence Award, BF Goodrich
`
`National Collegiate Invention Award, and DARPA Research Excellence Award
`
`in 1999.
`
`13. I am a 2007 Fellow of American Association for the Advancement in Science
`
`(AAAS) for my “distinguished contributions to the field of very large scale
`
`integrated (VLSI) systems.” The honor of being elected a Fellow of AAAS is
`
`given to those whose “efforts on behalf of the advancement of science or its
`
`applications are scientifically or socially distinguished.”
`
`14. I am also a 1999 Fellow of IEEE for my “contributions to the field of VLSI
`
`Design.”
`
`15. Further, the IEEE Electron Devices Society recognized me as an IEEE
`
`Distinguished Lecturer. Part of this recognition stems from the fact that I have
`
`presented over 100 invited talks at universities and companies around the world.
`
`Career Background
`2.
`16. After my baccalaureate degrees in Physics and Electrical Engineering, I worked
`
`for six years from 1976 to 1982 as a Senior R&D Engineer at Bharat Electronics
`
`Ltd. (“BEL”) in its Integrated Circuits Division. I designed several bipolar and
`
`CMOS analog and digital integrated circuits for consumer electronic systems.
`
`I was involved with the following chip development projects: (1) Raster-scan
`
`vertical deflection system microchip for TV display, (2) Sync processing and
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`horizontal deflection system microchip for TV display, (3) Video and audio IF
`
`stage IC’s for vestigial-AM and FM signal detection in TV receiver, and (4)
`
`High-gain audio amplifier microchip for TV audio stage. Several million
`
`commercial chips were fabricated based on these designs.
`
`17. After finishing my M.S. degree in Computer Science and while working
`
`towards my Ph.D. degree in Electrical and Computer Engineering, I worked
`
`during the summers of 1985 and 1986 as a member of the Technical Staff at
`
`AT&T Bell Laboratories. I was one of two engineers who started the Bell
`
`Laboratory Cones/Spruce project, a new behavioral synthesis and layout
`
`automation tool for rapid prototyping of digital circuits. The main contribution
`
`of this effort was to demonstrate how a restricted version of the C programming
`
`language could be used to model digital hardware, long before engineers
`
`developed commercial hardware description language (HDL) software tools
`
`like Verilog and System C.
`
`18. Since finishing my Ph.D. from the University of Illinois at Urbana-Champaign
`
`in 1988, I have worked at the University of Michigan in the Department of
`
`Electrical Engineering and Computer Science, where I was promoted to the
`
`rank of a full professor in 1998. I have supervised 21 Ph.D. students and over
`
`35 students studying for their M.S. in Electrical Engineering. I have also
`
`mentored 12 international undergraduate students and 12 visiting professors
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`and postdocs in my research group to foster global collaboration and outreach
`
`activities.
`
`19. I spent my sabbatical at Stanford University, University of California at
`
`Berkeley, and NTT Basic Research Laboratory in Japan in 1996 and 1997.
`
`20. In 2007 and 2008, I served as the lead program director for the Emerging
`
`Models and Technologies program, part of the National Science Foundation’s
`
`(NSF) Directorate for Computer and Information Science and Engineering
`
`(CISE). In this role, I managed research grants in various disciplines—such as
`
`Nanoelectronic Modeling, Quantum Computing, and Biologically Inspired
`
`Computing—overseeing an annual operating budget of approximately $18
`
`million.
`
`21. In 2009, I served as a program director for NSF’s Engineering Directorate
`
`where I managed research in three disciplines: Adaptive Intelligent Systems
`
`(Machine Learning); Quantum, Molecular, and High-Performance Modeling;
`
`and Electronic and Photonic Devices.
`
`22. In my three years of service to the United States government, I participated in
`
`several NSF programs such as Cyber-Enabled Discovery and Innovation (CDI),
`
`Expeditions in Computing, Major Research Instrumentation (MRI), Computing
`
`Research Infrastructure (CRI) and Cyber Physical Systems (CPS). I also
`
`worked with several managers and administrators of NSF, the Defense Advance
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Research Projects Agency (DARPA), the Army Research Office (ARO), the
`
`Office of Naval Research (ONR), and the Air Force Office of Scientific
`
`Research (AFOSR) to launch several major research initiatives at the national
`
`level.
`
`23. During my 27 years as a professor, I have regularly taught the following
`
`graduate-level courses: 1) VLSI System Design, 2) Optimization and Synthesis
`
`of VLSI Layout, 3) Testing of Digital Circuits and Systems, 4) Advanced
`
`Computer Architectures, 5) Nanocircuits and Nanoarchitectures, 6) Ultra-Low-
`
`Power Subthreshold CMOS Circuits, and 7) Terahertz Technology and
`
`Applications. In that same period, I have also regularly taught the following
`
`undergraduate-level courses: 1) Introduction
`
`to Digital Logic Design
`
`(sophomore level), 2) Digital Integrated Circuit Design (junior level), and 3)
`
`VLSI System Design (senior level).
`
`24. My experience with the design of computer systems is also evident from the
`
`subject matter of the courses I have taught. For example, every year since 1991,
`
`I have taught a major design experience (“MDE”) course on VLSI Systems
`
`Design, taken by senior undergraduate and entry-level graduate students. As the
`
`main design component of the course, each team of four to five students must
`
`design a fully-customized 16-bit RISC microprocessor for the given instruction
`
`set architecture. After completing the processor, students must develop an
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`interesting application for the processor by building embedded DRAM, SRAM
`
`and ROM and connecting them with the microprocessor through buses. The
`
`main goal of this VLSI design course is to give students hands-on design
`
`experience for a large chip design project, as mandated by the Accreditation
`
`Board for Engineering and Technology (ABET).
`
`25. Over the last 30 years, I have trained and supervised 21 doctoral students and
`
`35 Master’s students, many of whom now work in the microelectronics and
`
`semiconductor industries. To promote international collaboration, I hosted 10
`
`visiting professors from various parts of the world. In addition to numerous
`
`domestic students, I have also advised 12 undergraduate students from various
`
`countries providing
`
`them opportunity
`
`to gain undergraduate research
`
`experience.
`
`Relevant Publications
`3.
`26. I have published or co-published 13 books, 125 journal articles, 183 peer-
`
`reviewed conference papers, and 4 book chapters. A full list of my publications
`
`can be found in my CV. Ex. 1002.
`
`27. My first book, published in 1996, relates to testing and testable designed for
`
`Random-Access Memories (“RAM”). I also published a book relating to the
`
`layout and automated-testing of very-large-scale
`
`integration (“VLSI”)
`
`integrated circuits (“IC”)—which involves the combination of thousands of
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`transistors into a single chip—in 1999, and then I published a “Handbook for
`
`VLSI Routing” in 2018, prioritizing the discussion of serial and parallel modes
`
`of transmitting data. My other books generally relate to fault tolerances in
`
`RAM (2002), digital logic design (2018) and Neuromorphic Computing (2018),
`
`the last of which generally looks to biology to inform the development of
`
`algorithms and the design of certain semiconductor architectures.
`
`28. I have published numerous articles and journal publications advancing the state
`
`of the art for semiconductor and memory design.
`
`29. I have conducted significant research into the design of VLSI systems,
`
`especially those built using CMOS technology, which is a complementary
`
`metal–oxide–semiconductor fabrication technique that allows the creation of
`
`low-power integrated circuits. Many of my publications focused on the optimal
`
`layout of various components in a CMOS VLSI semiconductor device,
`
`including: “Hexagonal Array Machine for Multi-Layer Wire Routing,”
`
`published in 1990 with the IEEE Transactions on Computer-Aided Design of
`
`Integrated Circuits and Systems Journal; “VLSI Cell Placement Techniques,”
`
`published in 1991 with the ACM Computing Surveys Journal; “Layout
`
`Optimization for Yield Enhancement
`
`in On-Chip VLSI/WSI Parallel
`
`Processing,” published in 1992 with the IEE Proceedings-E: Computers and
`
`Digital Techniques Journal; and “CHiRPS: A General-area Parallel Multi-layer
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Routing System,” published in 1995 with the IEE Proceedings-E: Computers
`
`and Digital Techniques Journal. The last publication demonstrated how extreme
`
`scale fine grained parallel processing can be achieved by using simple
`
`processing elements with ALU and local memory to reconfigure them several
`
`times with flexible interconnections to perform various types of VLSI routing
`
`algorithms such as maze routing, channel routing, switchbox routing, and area
`
`routing. The content-addressable parallel processing CHiRPS architecture is
`
`also suited to accelerate general class of pixel-level image processing.
`
`30. I have also conducted research on reconfigurable processor architectures
`
`comprising programmable logic blocks and on-chip memories interconnected
`
`by reconfigurable buses, as can be found in my publication: “DA Techniques
`
`for PLD and FPGA Based Systems,” Integration, the International VLSI
`
`Journal, Vol. 17, Dec. 1994, pp. 191-240.
`
`31. I have also conducted significant research into memories that are commonly
`
`used with processors. For example, I published an article “Methodologies for
`
`Testing Embedded Content-Addressable Memories” in 1988 with the “IEEE
`
`Transactions on Computer-Aided Design of Integrated Circuits and Systems”
`
`journal, which discusses techniques for testing content-addressable memories
`
`(“CAMs”) in dynamic RAMs (“DRAMs”). Specific to DRAMs, I have also
`
`published articles on: “A Reconfigurable Parallel Signature Analyzer for
`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Concurrent Error Correction in Dynamic Random-Access Memory” (1990);
`
`“Circuit Behavior Modeling and Compact Testing Performance Evaluation”
`
`(1991); and “On Restructuring of Hexagonal Arrays” (1992), “Restructuring of
`
`Square Processor Arrays by Built-in Self-Repair Circuit” (1993). I have also
`
`published a number of articles on static RAMs, including “Technology and
`
`Layout Related Testing in Static Random-Access Memories” in 1994 in the
`
`Journal of Electronic Testing: Theory and Applications.
`
`32. I have also been selected for and published a number of peer-reviewed
`
`conference publications. These include, among others: “Evaluation of Three
`
`Interconnection Networks for CMOS VLSI Implementation,” published in
`
`1986 with the Proceedings IEEE International Conference on Parallel
`
`Processing; “Hexagonal Array Machine for Multi-Layer Wire Routing,”
`
`published in 1989 with the Proceedings IEEE International Conference on
`
`Computer-Aided Design; “On Restructuring of Hexagonal Processor Arrays,”
`
`published in 1991 with the IEEE Intl. Conf. on Defect and Fault Tolerance in
`
`VLSI Systems; “Processor Array Self-Reconfiguration by Neural Networks,”
`
`published in 1992 with the IEEE International Wafer Scale Integration; and
`
`“Parallel VLSI-Routing Models for Polymorphic Processors Array (embedded
`
`tutorial),” published in 1997 with the Proceedings on IEEE International VLSI
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Conference. Each of these publications examined or related to the interconnect
`
`structures on VLSI semiconductor devices.
`
`Patents
`4.
`33. I have been a named inventor on ten granted U.S. patents, and I am the named
`
`inventor on three U.S. patent applications currently being reviewed. A full list
`
`of my patents can be found in my CV. Ex. 1002.
`
`34. For example, I am named inventor on U.S. Patent number 5,903,170, granted
`
`on June 3, 1997 and titled “Digital Logic Design Using Negative Differential
`
`Resistance Diodes and Field-Effect Transistors.” My invention related to the
`
`design of digital logic gates using negative differential-resistance diodes and
`
`metal oxide semiconductor field effect
`
`transistors (“MOSFETS”) or
`
`heterostructure field effect transistors.
`
`35. As another example, I am named inventor on U.S. Patent number 6,323,709,
`
`granted on November 21, 2001 and titled “High-speed, compact, edge-
`
`triggered, flip-flop circuit.” Whereas static flips use functional logic gates to
`
`temporarily store data in a flip-flop circuit, edge-triggered flip-flop circuits use
`
`a dynamic approach that is more flexible. My invention introduced a
`
`specialized latch circuit, which improved circuit reliability as compared to
`
`prior-art dynamic flip-flops.
`
`36. Other technologies in which I have been listed as named inventor include:
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`(a) Ultra-low-power CMOS Static Random Access Memory Cell having
`
`Improved Write Margin for use in Ultra-Low Power Application,
`
`disclosed in U.S. patent number 9,627,042;
`
`(b) Resistive RAM single-cell and multi-cell memory technology,
`
`disclosed in U.S. patent number 9,111,613;
`
`(c) CMOS circuit techniques, such as Method and Apparatus to Improve
`
`Noise Tolerance of Dynamic Circuits, disclosed in U.S. patent number
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`7,088,143;
`
`(d) Terahertz technology such as Terahertz Analog-to-Digital Converter
`
`Employing Active-Controlled Spoofed Surface Plasmon Polariton
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`Architecture, disclosed in U.S. patent number 9,341,921;
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`(e) Mach-Zehnder Interferometer Having a Doubly-Corrugated Spoofed
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`Surface Plasmon Polariton Waveguide, disclosed in U.S. patent number
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`9,557,223;
`
`(f) Dynamic Terahertz Switching Device Comprising Sub-Wavelength
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`Corrugated Waveguides and Cavity that Utilizes Resonance and
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`Absorption for Attaining On and Off States, disclosed in U.S. patent
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`number 8,842,948;
`
`(g) Dynamic Terahertz Switch Using Periodic Corrugated Structures,
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`disclosed in U.S. patent number 8,837,036; and
`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`
`
`(h) Metamaterial Sensors Platform for Terahertz Sensing, disclosed in U.S.
`
`patent number 9,551,655.
`
`III. UNDERSTANDING OF PATENT LAW
`37. I understand that for purposes of this proceeding, prior art to the ’593 patent
`
`includes patents and printed publications in the relevant art that predate the
`
`alleged priority date of the ’593 patent.
`
`38. I understand that claims in an IPR are construed under the case Phillips v. AWH
`
`Corp., 415 F.3d 1303 (Fed. Cir. 2005), decided by the Federal Circuit in 2005.
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`Under the rule in Phillips, words of claims are given their plain and ordinary
`
`meaning as understood by a person of ordinary skill in the art in view of the
`
`specification and prosecution history, unless those sources show an intent to
`
`depart from such meaning.
`
`39. I understand that a claim is invalid if it is anticipated or obvious. Anticipation
`
`of a claim requires that every element be disclosed expressly or inherently in a
`
`single prior art reference, arranged in the prior art reference as arranged in the
`
`claim. Obviousness of a claim requires that the claim be obvious from the
`
`perspective of a POSITA at the time the alleged invention was made. I
`
`understand that a claim may be obvious solely in view of a single reference, or
`
`may be obvious from a combination of two or more prior art references.
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`
`
`40. I understand that an obviousness analysis requires an understanding of the scope
`
`and content of the prior art, any differences between the alleged invention and
`
`the prior art, and the level of ordinary skill in evaluating the pertinent art.
`
`41. I also understand that the following factors are relevant to obviousness:
`
`(i)
`
`Combining prior art elements according to known methods to yield
`
`predictable results;
`
`(j)
`
`Simple substitution of one known element for another to obtain
`
`predictable results;
`
`(k) Use of known technique to improve similar devices (methods, or
`
`products) in the same way;
`
`(l) Applying a known technique to a known device (method, or product)
`
`ready for improvement to yield predictable results;
`
`(m) “Obvious to try” – choosing from a finite number of identified,
`
`predictable solutions, with a reasonable expectation of success;
`
`(n) Known work in one field of endeavor may prompt variations of it for
`
`use in either the same field or a different one based on design incentives
`
`or other market forces if the variations are predictable to one of ordinary
`
`skill in the art;
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`
`
`(o)
`
`Some teaching, suggestion, or motivation in the prior art that would
`
`have led one of ordinary skill to modify the prior art reference or to
`
`combine prior art reference teachings to arrive at the claimed invention.
`
`42. I further understand that a claim is obvious if it unites old elements with no
`
`change to their respective functions, or it alters prior art by mere substitution of
`
`one element for another known in the field, and that combination yields
`
`predictable results. While it may be helpful to identify a reason for this
`
`combination, common sense should guide and no rigid requirement of finding
`
`a teaching, suggestion, or motivation to combine is required. When a product
`
`is available, design incentives and other market forces can prompt variations of
`
`it, either in the same field or different one. If a person having ordinary skill in
`
`the relevant art can implement a predictable variation, obviousness likely bars
`
`its patentability. For the same reason, if a technique has been used to improve
`
`one device and a person having ordinary skill in the art would recognize that it
`
`would improve similar devices in the same way, using the technique is obvious.
`
`I understand that a claim may be obvious if common sense directs one to
`
`combine multiple prior art references or add missing features to reproduce the
`
`alleged invention recited in the claims.
`
`43. I further understand that certain factors may support or rebut the obviousness
`
`of a claim. I understand that such secondary considerations include, among
`
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`Declaration of Dr. Pinaki Mazumder Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`
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`other things, commercial