`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________________________________________________
`
`UNIVERSAL IMAGING INDUSTRIES, LLC
`Petitioner
`
`v.
`
`LEXMARK INTERNATIONAL, INC.
`Patent Owner
`
`_____________________________________________________________
`
`Patent No. 9,245,591
`
`_____________________________________________________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 9,245,591
`
`
`
`
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`
`
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`
`
`TABLE OF CONTENTS
`
`INTRODUCTION ................................................................................ 1
`
`I.
`
`II. MANDATORY NOTICES ................................................................... 1
`
`III. FEE AUTHORIZATION ...................................................................... 2
`
`IV. GROUNDS FOR STANDING ............................................................. 2
`
`V.
`
`PRECISE RELIEF REQUESTED ........................................................ 2
`
`VI. SUMMARY OF THE ‘591 PATENT .................................................. 3
`
`A.
`
`B.
`
`Overview of the Technology ............................................................ 3
`
`Overview of the ‘591 Patent ............................................................. 3
`
`VII. LEVEL OF SKILL ............................................................................... 4
`
`VIII. CLAIM CONSTRUCTION .................................................................. 4
`
`IX. OVERVIEW OF THE PRIOR ART ..................................................... 4
`
`A.
`
`B.
`
`C.
`
`Blood ................................................................................................. 4
`
`I2C Spec ............................................................................................ 6
`
`Bruce ................................................................................................. 8
`
`X. DETAILED EXPLANATION OF GROUNDS ................................... 9
`
`A.
`
`Ground 1: Claims 1-16 are Obvious in View of Blood, I2C Spec,
`
`and Bruce 9
`
`1. Reasons to combine .......................................................................... 9
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`2. Claim 1 ............................................................................................ 10
`
`i
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`3. Claim 2 ............................................................................................ 14
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`4. Claim 3 ............................................................................................ 15
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`5. Claim 4 ............................................................................................ 16
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`6. Claim 5 ............................................................................................ 16
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`7. Claim 6 ............................................................................................ 17
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`8. Claim 7 ............................................................................................ 17
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`9. Claim 8 ............................................................................................ 23
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`10.
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`11.
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`12.
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`13.
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`14.
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`15.
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`16.
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`17.
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`Claim 9 ........................................................................................ 24
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`Claim 10 ...................................................................................... 25
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`Claim 11 ...................................................................................... 26
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`Claim 12 ...................................................................................... 32
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`Claim 13 ...................................................................................... 32
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`Claim 14 ...................................................................................... 33
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`Claim 15 ...................................................................................... 34
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`Claim 16 ...................................................................................... 34
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`XI. CONCLUSION ................................................................................... 34
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`
`
`
`
`
`
`ii
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`
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`
`
`Ex. 1001
`Ex. 1002
`Ex. 1003
`Ex. 1004
`Ex. 1005
`Ex. 1006
`Ex. 1007
`
`
`EXHIBIT LIST
`
`U.S. Patent 9,245,591 to Lexmark
`Declaration of Dr. Harry Direen
`U.S. Patent 3,993,867 to Blood
`I2C-Bus Specification
`U.S. Patent 5,822,251 to Bruce
`Curriculum vitae of Dr. Harry Direen
`File History of U.S. Patent 9,245,591
`
`
`iii
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`
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`
`
`I.
`
`INTRODUCTION
`
`Universal Imaging Industries, LLC (“Universal” or “Petitioner”), requests
`
`inter partes review of Claims 1-16 of U.S. Patent No. 9,245,591 (“the ‘591”
`
`Patent, Ex. 1001), currently assigned to Lexmark International, Inc., in accordance
`
`with 35 U.S.C. §§ 311-319 and 37 C.F.R. §§ 42.100 et seq. This Petition presents
`
`non-cumulative grounds of invalidity that the U.S. Patent and Trademark Office
`
`(“PTO”) did not consider during prosecution. These grounds are each likely to
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`prevail, and this Petition should be granted. The challenged claims should each be
`
`cancelled.
`
`II. MANDATORY NOTICES
`Real Parties-in-Interest: Petitioner identifies the following real parties-in-
`
`interest: Universal Imaging Industries, LLC.
`
`Related Matters: Patent Owner has asserted the ‘591 Patent against
`
`Petitioner in Lexmark International, Inc. v. Universal Imaging Industries, LLC,
`
`M.D. of FL, 8:18-cv-01047-EAK-AEP. Patent Owner has also asserted U.S.
`
`Patent Nos. 9,400,764; and 9,837,136 in the related action. Petitioner is
`
`concurrently filing IPR petitions for those patents.
`
`The ‘591 Patent is a continuation-in-part of the ‘764 Patent. The ‘136 Patent
`
`is a continuation of the ‘591 Patent. This Petition and the IPRs directed to the ‘764
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`and ‘136 Patents rely on the same prior art
`
`1
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`
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`
`
`
`
`Lead Counsel: Woodrow
`
`Pollack
`
`(Reg.
`
`No.
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`58,908)
`
`(wpollack@shutts.com), Shutts & Bowen, LLP, 4301 W Boy Scout Blvd, Suite
`
`300, Tampa, FL 33607.
`
`Back-up Counsel: Ryan
`
`Santurri
`
`(Reg.
`
`No.
`
`61,894)
`
`(rsanturri@allendyer.com), Allen, Dyer, Doppelt + Gilchrist, PA, PO Box 3791,
`
`Orlando, FL 32802.
`
`Service Information:
`
`Please address all correspondence to counsel at the
`
`addresses shown above. Petitioner consents to electronic service by email to
`
`wpollack@shutts.com.
`
`III. FEE AUTHORIZATION
`The PTO is authorized to charge $31,100 to Deposit Account 50-4000 for
`
`the fee set forth in 37 C.F.R. § 42.15(a), and any additional fees that might be due
`
`in connection with this Petition.
`
`IV. GROUNDS FOR STANDING
`Petitioner certifies that the ‘591 Patent is available for IPR and Petitioner is
`
`not barred or estopped from requesting IPR on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED
`
`Petitioner respectfully requests review and cancellation of Claim 1-16 of the
`
`‘591 Patent on the below grounds:
`
`2
`
`
`
`
`
`Ground Claims
`
`1-16
`
`1
`
`
`
`Basis
`
`§ 103
`
`Prior art
`
`Blood, I2C Spec, and Bruce
`
`VI. SUMMARY OF THE ‘591 PATENT
`A. Overview of the Technology
`The ‘591 Patent relates communication between circuitry using a single
`
`
`
`signal line.
`
`B. Overview of the ‘591 Patent
`The ‘591 Patent is generally directed to a memory module that limits the
`
`voltage on a signal line following the reception of a command to indicate a busy
`
`condition, an error condition, or some other condition. According to the ‘591
`
`Patent, a processing device can send a signal out to a memory device over a signal
`
`line while at the same tie the memory device can send a busy, error, or other
`
`condition back to the processing device on the same signal line.
`
`Bidirectional signaling on a line is not novel. U.S. Patent 3,993,867
`
`(“Blood”), Ex. 1003, teaches bidirectional signaling on a single line. Petitioner
`
`asks the Board to institute review of claims 1-16 of the ‘591 Patent.
`
`
`
`As explained in detail in the corresponding Declaration of Dr. Harry Direen
`
`3
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`
`
`
`
`(attached as Ex. 10021), and addressed in further detail below, the challenged
`
`claims of the ‘591 Patent would not have been considered new or nonobvious to a
`
`person of ordinary skill in the art at the time of filing.
`
`VII. LEVEL OF SKILL
`
`
`At the time of the priority date of the ‘591 Patent, a person of ordinary skill
`
`in the art would have a bachelor’s degree in electrical and/or computer engineering
`
`with training and one or more years of experience in embedded systems, including
`
`both hardware and embedded software design. Ex. 1002, Direen Decl. at ¶¶ 25-28.
`
`VIII. CLAIM CONSTRUCTION
`
`The grounds in this Petition render obvious the challenged claims under both
`
`the broadest reasonable interpretation standard and the Phillips standard. To
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`resolve the grounds presented in this Petition, Petitioner does not believe any term
`
`requires construction.
`
`IX. OVERVIEW OF THE PRIOR ART
`A. Blood
`Blood issued November 23, 1976 and is prior art to the ‘591 Patent under 35
`
`
`
`U.S.C. § 102. Blood was not relied upon during prosecution of the ‘591 Patent.
`
`
`
`Blood discloses full duplex transmission of a digital signal on a signal line.
`
`
`1 Ex. 1002 includes Dr. Direen’s declaration, as well as a claim chart identified as
`Ex. 1002-A.
`
`4
`
`
`
`
`
`Blood at 2:12-23 (“Fig. 1 shows in a block diagram form a full duplex digital
`
`transmission system that comprises a single transmission line or bus 11 connecting
`
`a first station A to a second station B wherein each station includes a
`
`transmitter/receiver pair.”). Each transmitter or receiver may be any system or
`
`subsystem component, including “memories, registers, central processing units,
`
`and the like that function as a transmitter or receiver of digital signals.” Id. at
`
`2:27-29. Blood discloses circuitry that combines the digital signals into different
`
`states, in order to facilitate full duplex transmission. Id. at Abstract (“The circuit
`
`includes means that combine the incoming and outgoing digital signals in the
`
`signal line to form a composite multi-level signal which shifts between
`
`predetermined amplitude levels and means that recover the incoming digital
`
`signals from the composite signal.”). This provides for full duplex transmission.
`
`Id. (“Using such a circuit a full duplex transmission system of a plurality of
`
`stations connected to a common single line is provided.”). “[A]t any given
`
`moment there may exist simultaneously outgoing digital signals from station A to
`
`station B and incoming digital signals from station A to station B and the system
`
`can handle the incoming and outgoing digital signals simultaneously.” Id. at 2:37-
`
`42.
`
`
`
`Fig. 3 of Blood depicts signals “M” and “N” being simultaneously
`
`transmitted over line 11:
`
`5
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`
`
`
`
`
`
`Signal N is the outgoing signal from transmitter T1 in station A, which is received
`
`by station B’s receiver R2. Signal M is the output of station B’s transmitter, which
`
`is the incoming signal for station A.
`
`
`
`The signal on line 11 (“O”) is the “net composite of the outgoing and
`
`incoming signals in the signal line is a scalar or an analog addition of the two
`
`signals.” Id. at 4:35-39. “When both transmitters send, then the voltage level at
`
`the transmission line 11 shifts between three levels, as illustrated in Fig. 3; O.” Id.
`
`at 5:53-55.
`
`
`
`Thus, Blood discloses a “low,” “intermediate,” and “high” state for
`
`transmission across a single line.
`
`B.
`I2C Spec
`Version 2.1 of the I2C-Bus Specification (“the I2C Spec”), Ex. 1004, was
`
`
`
`published in January, 2000 and is prior art to the ‘591 Patent under 35 U.S.C. §
`
`6
`
`
`
`
`
`102(b). Phillips Corporation n/k/a NXP published the I2C Spec as document order
`
`number 9398 393 40011. The I2C Spec was submitted in an Information
`
`Disclosure Statement during prosecution of the ‘591 Patent.
`
`
`
`Phillips Semiconductors developed the I2C bus in the early 1980s. Ex. 1002,
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`Direen Decl. at ¶ 52. Version 2.1 of the specification was published in January,
`
`2000, well before the priority date of the ‘591 Patent. Id. at ¶ 53.
`
`
`
`Figure 1 of the I2C standard shows an example of an I2C bus applications.
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`I2C is a bi-directional, two wire serial bus which has a serial data line (SDA) and a
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`serial clock line (SCL). Each device connected to the bus is software addressable
`
`by a unique address and simple master/slave relationships exist at all times.
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`
`
`I2C Spec discloses a plurality of signal lines, including SDA, SCL, and
`
`DLEN as shown in Figure 19:
`
`
`
`7
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`
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`
`
`See also id. at 18 (“However, a third bus line called DLEN must then be
`
`connected…”).
`
`
`
`C. Bruce
`Bruce issued on October 13, 1998 and is prior art under 35 U.S.C. § 102.
`
`Bruce was not relied upon during prosecution of the ‘591 Patent.
`
`
`
`Bruce discloses an expandable flash-memory mass-storage using shared
`
`buddy lines, and intermediate flash-bus between device-specific buffers and flash-
`
`intelligent DMA controllers. Ex. 1005, Bruce at Title. Bruce discloses memory
`
`devices with multiple memory cells and multiple signal lines for communicating
`
`with the device. Id. at Fig. 2. The memory includes a busy condition status line.
`
`Id. at Fig. 1.
`
`
`
`Bruce discloses a busy signal provided by a memory chip. Id. at 1:66-2:3
`
`(“A busy signal is usually provided by each flash-memory chip to indicate when
`
`the read, write, or erase operation has completed. The busy signal allows a local
`
`8
`
`
`
`
`
`processor to continue with other tasks while the flash-memory integrated circuit
`
`chip performs the flash operation.”).
`
`
`
`Bruce further discloses a plurality of signal lines. Id. at 2:57-60 (“The flash
`
`bus has shared lines that transmit the sequence of command bytes and address
`
`bytes from the flash-specific DMA controller. The shared lines also transmit data
`
`bytes from the flash-specific DMA controller for the host interface.”).
`
`X.
`
`
`
`DETAILED EXPLANATION OF GROUNDS
`
`A. Ground 1: Claims 1-16 are Obvious in View of Blood, I2C Spec,
`and Bruce
`1. Reasons to combine
`A POSITA would have found it obvious to combine Blood, I2C Spec, and
`
`Bruce. Ex. 1002, Direen Decl. at ¶¶ 49-50. See also generally Ex. 1002-A. Blood
`
`applies to memory devices with multiple memory cells and multiple signal lines
`
`for communicating with a processing device. The memory device is assumed to
`
`have a “busy” condition that can be communicated back to the processing device.
`
`Bruce discloses a memory device having a busy condition that is communicated
`
`back to a processing device. Blood discloses an improved way for communicating
`
`in a full duplex mode on a signal line. A POSITA would have looked to combine
`
`these disclosures to improve the performance and capabilities of these memory
`
`devices.
`
`
`
`I2C Spec additionally deals with signaling on a shared bus, and is in fact the
`
`9
`
`
`
`
`
`“de facto world standard” for shared bus addressing and communication. Ex.
`
`1004, I2C Spec at 3. As such, a POSITA would also rely on the teachings of I2C
`
`Spec to implement memory chips communicating on an I2C bus.
`
`2. Claim 1
`a)
`“A memory module, comprising;”
`
`
`
`To the extent it is limiting, Blood and Bruce each disclose this preamble.
`
`Ex. 1002-A at Claim 1; Ex. 1003, Blood at 2:23-39; Ex. 1005, Bruce at Fig. 1.
`
`b)
`
`“a plurality of memory cells; and”
`
`
`
`Blood discloses a plurality of memory cells. Ex. 1002-A at Claim 1; Ex.
`
`1003, Blood at 2:23-39 (“It is to be understood that ‘transmitter’ and ‘receiver’
`
`mentioned in this specification are used as generic expressions to denote many
`
`diverse systems and subsystem components, such as teletypewriters, CRT display
`
`devices, memories, registers, central processing units and the like that function as
`
`a transmitter or receiver of digital signals.”) (emphasis added).
`
`
`
`Bruce additionally discloses a plurality of memory cells. Ex. 1002-A at
`
`Claim 1; Ex. 1005, Bruce at Figs 1 & 2.
`
`c)
` “a plurality of signal lines for communicating with a
`processing device,”
`I2C Spec discloses a plurality of signal lines for communicating with a
`
`
`
`processing device. Ex. 1002, Direen Decl. at ¶ 51; Ex. 1002-A at Claim 1; I2C
`
`Spec at Fig. 19 (disclosing SDA, SCL, and DLEN). Blood also a plurality of
`
`10
`
`
`
`
`
`signal lines for communicating with a processing device. Ex. 1002-A at Claim 1;
`
`Ex. 1003, Blood at 2:57-60 (“The flash bus has shared lines that transmit the
`
`sequence of command bytes and address bytes from the flash-specific DMA
`
`controller. The shared lines also transmit data bytes from the flash-specific DMA
`
`controller for the host interface.”).
`
`d)
` “the memory module configured such that upon
`encountering a first condition while processing a command
`received by the memory module, the memory module limits a
`voltage on a first signal line of the plurality of signal lines to
`be no more than an intermediate voltage greater than voltage
`levels corresponding to a binary zero state and less than
`voltage levels corresponding to a binary one state for a period
`of time for indicating an occurrence of the first condition”
`
`
`
`Blood discloses this limitation. Ex. 1002, Direen Decl. at ¶¶ 34-36; Ex.
`
`1002-A at Claim 1. Blood discloses a full-duplex transmission of a digital signal
`
`on a signal line. The digital signal on the line is a multi-level digital signal as
`
`shown in Blood Fig. 3. The voltage signal on line 11 operates between a low
`
`voltage level and a high voltage level with intermediate voltage levels as seen as
`
`signal “O” of Fig. 3.
`
`
`
`Bruce discloses a first condition, namely a busy condition. Ex. 1005, Bruce
`
`at 3:19-21 (“In further aspects of the invention each flash-memory chip outputs a
`
`busy signal to indicate when a flash operation is in progress within the flash-
`
`memory chip.”).
`
`
`
`A busy signal on the memory going low will cause the line 11 voltage to go
`
`11
`
`
`
`
`
`to an intermediate voltage halfway between the high and low voltages on line 11
`
`when the processor side of the line is in the high state. Ex. 1002-A at 5-7. When
`
`the processor side of the line is in the low state and the memory busy signal is in
`
`the low state, line 11 will be at the low voltage, which is less than the intermediate
`
`voltage. This condition occurs during the time the memory is in a “busy” state.
`
`“When both transmitters send, then the voltage level at the transmission line 11
`
`shifts between three levels, as illustrated in Fig. 3; O.” Blood at 5:53-55.
`
`e)
` “wherein the memory module is configured to receive a
`first signal on the first signal line, and during the period of
`time the memory module limits a voltage on the first signal
`line to be no greater than the intermediate voltage, a voltage
`level on the first signal line corresponding to the binary zero
`state is interpreted by the memory module as a binary zero
`state of the first signal and the intermediate voltage on the
`first signal line is interpreted by the memory module as a
`binary one state of the first signal such that during the period
`of time, the memory module receives the first signal on the
`first signal line while at the same time the memory module
`communicates the occurrence of the first condition on the
`first signal line to the processing device,”
`
`
`
`Blood discloses this limitation. Ex. 1002 Direen Decl at ¶¶ 33-38. While the
`
`memory module limits voltage on the first signal line to be no greater than the
`
`intermediate voltage, Blood interprets a voltage level on the first signal line
`
`corresponding to the binary zero state as a binary zero. Ex. 1003, Blood at 5:44-49
`
`(“This being the case, referring to the voltage level at the transmission line, it is
`
`evident that when neither the transmitter of station A nor the transmitter of station
`
`12
`
`
`
`
`
`B sends digital signals, then no current is present in the transmission line 11.
`
`Accordingly, the voltage at the transmission line is zero volts.”).
`
`
`
`While the memory module limits voltage on the first signal line to be no
`
`greater than the intermediate voltage, Blood interprets an intermediate voltage
`
`level on the first signal line as a binary one state of the first signal. Id. at 6:3-12
`
`(“By supplying ground or 0 volts for Vcc and -5.2 volts for VEE and providing
`
`appropriate impedances for the various active and passive elements, it was possible
`
`to provide three levels of voltages to the transmission line, for example 0 volts, -
`
`0.8 volts, and -1.6 volts, and apply to input x of differential amplifier DA and
`
`derive two levels of voltages, namely -0.4 volts and -1.2 volts, from the output of
`
`the first active element Q2 of second switch S2 and apply the same to second input
`
`terminal y of differential amplifier DA.”) See also id. at 6:28-30 (“The line signal
`
`shifts between three levels, namely 0, -0.8 and -1.6 volts when both outgoing and
`
`incoming digital signals of 0s and 1s are present.”).
`
`
`
`Blood discloses the memory module communicates the occurrence of the
`
`first condition on the first signal line to the processing device. Id. at 6:37-43 (“In
`
`summary then, it has been shown that utilizing a novel circuitry of the type
`
`illustrated in Fig. 2, in a general block diagram form, and in a specific illustrative
`
`embodiment in Fig. 4, a digital signal transmission system can be rendered
`
`operative in a full duplex mode, over single signal path 11, synchronously or
`
`13
`
`
`
`
`
`asynchronously.”). This is also demonstrated through visual comparison of the
`
`‘597 Patent’s Fig. 10 and Blood’s Fig. 3:
`
`
`
`
`f)
`“wherein the first signal comprises a clock signal and
`the first condition comprises a busy condition,”
`
`
`
`It is well-known for a device to send a busy condition in response to a signal
`
`on the clock line. Ex. 1004, I2C Spec at 8 (“Bus clock signals from a master can
`
`only be altered when they are stretched by a slow-slave device holding-down the
`
`clock line, or by another master when arbitration occurs.”); Id. at 10 (“If a slave
`
`can’t receive or transmit another complete byte of data until it has performed some
`
`other function, for example servicing an internal interrupt, it can hold the clock line
`
`SCL LOW to force the master into a wait state.”). As such, this claim is obvious in
`
`light of Blood, the I2C Spec, and Bruce.
`
`3. Claim 2
`a)
`“The memory module of claim 1, wherein upon
`encountering a second condition while processing
`the
`command, the memory module limits a voltage on a second
`signal line of the plurality of signal lines to be no more than a
`
`14
`
`
`
`
`
`second intermediate voltage greater than voltage levels
`corresponding to the binary zero state and less than voltage
`levels corresponding to the binary one state for a second
`period of time for indicating an occurrence of the second
`condition, wherein the memory module is configured to
`receive a second signal on the second signal line, and during
`the second period of time the memory module limits a voltage
`on the second signal line to be no greater than the second
`intermediate voltage, a voltage level on the second signal line
`corresponding to the binary zero state is interpreted by the
`memory module as a binary zero state of the second signal
`and the second intermediate voltage on the second signal line
`is interpreted by the memory module as a binary one state of
`the second signal such that during the second period of time,
`the memory module receives the second signal on the second
`signal line while at the same time the memory module
`communicates the occurrence of the second condition on the
`second signal line to the processing device, and wherein the
`second signal comprises an address-data signal and the
`second condition comprises an error condition.”
`
`
`
`Blood teaches this functionality for duplex communication on a single line.
`
`It is obvious to a POSITA to apply the technology from a single line to a second
`
`line. Ex. 1002-A at Claim 2. Indeed, an error condition is well-known to a
`
`POSITA. Id. The ‘591 Patent itself identifies this as known in the art. Ex. 1001,
`
`‘591 Patent at 1:3-7.
`
`4. Claim 3
`a)
`“The memory module of claim 1, further comprising at
`least one electrical component coupled between the first
`signal line and a ground potential such that the memory
`module passes current through the at least one electrical
`component for limiting the voltage on the first signal line to
`be no more than the intermediate voltage;”
`
`
`
`Blood discloses at least one electrical component coupled between the first
`
`15
`
`
`
`
`
`signal line and a ground potential for limiting the voltage to be no more than the
`
`intermediate voltage. Ex. 1002-A at Claim 3; Ex. 1003, Blood at Fig. 1; 3:28-34.
`
`
`
`Blood’s preferred embodiment depicts R6 and Q7 as electrical components
`
`coupled between the first signal line and a ground potential (VEE) such that the
`
`memory module passes current through the at least one electrical component for
`
`limiting the voltage on the first signal line to be no more than the intermediate
`
`voltage. Ex. 1003, Blood at Fig. 4.
`
`5. Claim 4
`a)
`the
`“The memory module of claim 3, wherein
`intermediate voltage is based at least in part upon a resistance
`of the at least one electrical component.”
`
`
`
`Blood discloses this limitation as disclosed in Claim 3. Ex. 1002-A at Claim
`
`4; Ex. 1003, Blood at 3:25-30 (“Current switch SI may be of any conventional
`
`design that converts its input, that is, the outgoing digital signals from transmitter
`
`TI, which may appear in the voltage form into current signals. The current signals
`
`are then applied to load impedances RL and RL’ to provide IR voltage drop.”).
`
`6. Claim 5
`a)
`“The memory module of claim 3, wherein the at least
`one electrical component comprises at least one resistor.”
`
`
`
`Blood discloses the at least one electrical component comprises at least one
`
`resistor. Ex. 1002-A at Claim 5 (“R6 is a resistor.”); Ex. 1003, Blood at 1:59-60
`
`(“The basic invention uses a summing resistor as a load resistor across the
`
`16
`
`
`
`
`
`transmission line at each terminal.”).
`
`7. Claim 6
`a)
`“The memory module of claim 3, wherein the at least
`one electrical component comprises at least one diode.”
`
`
`
`Blood discloses this limitation. Ex. 1002-A at Claim 6. It is well-known to
`
`a POSITA “that a bipolar junction transistor (BJT) is composed of back-to-back
`
`diodes.” Id. A POSITA also understands that a transistor may be operated as a
`
`switch and a resistor can be used to control current. Id. Blood discloses using
`
`different conventional electrical components
`
`to
`
`implement
`
`full duplex
`
`communication on the signal line. Ex. 1003, Blood at 3:25-30 (“Current switch S1
`
`may be of any conventional design that converts its input, that is, the outgoing
`
`digital signals from transmitter T1, which may appear in the voltage form into
`
`current signals. The current signals are then applied to load impedances RL and
`
`RL' to provide IR voltage drop.”).
`
`8. Claim 7
`a)
`“An apparatus, comprising:”
`
`
`
`To the extent it is limiting, Blood discloses this preamble. Ex. 1002-A at
`
`Claim 7; Ex. 1003, Blood at 2:23-39.
`
`b)
`“a first signal line for communicating clock and busy
`status information;”
`
`
`
`Blood discloses this limitation. Ex. 1002-A at Claim 7. Blood discloses a
`
`full-duplex transmission of a digital signal on a signal line. Blood’s Fig. 1
`
`17
`
`
`
`
`
`discloses a signal line, 11, for communicating information such as a clock and busy
`
`status information:
`
`
`
`The voltage signal on line 11 operates between a low voltage level and a high
`
`voltage level with intermediate voltage levels as seen as signal “O” of Fig. 3.
`
`
`
`I2C Spec additionally discloses a first signal line for communicating clock
`
`and busy status information. Ex. 1004, I2C Spec at 8 (“Bus clock signals from a
`
`master can only be altered when they are stretched by a slow-slave device holding-
`
`down the clock line, or by another master when arbitration occurs.”); Id. at 10 (“If
`
`a slave can’t receive or transmit another complete byte of data until it has
`
`performed some other function, for example servicing an internal interrupt, it can
`
`hold the clock line SCL LOW to force the master into a wait state.”).
`
`c)
` “a second signal line for communicating address, data
`and error status information; and”
`I2C Spec discloses a second signal line for communicating address, data and
`
`
`
`error status information. Ex. 1004, I2C Spec at 8 (“Both SDA and SCL are bi-
`
`directional lines, connected to a positive supply voltage via a current source or
`
`pull-up resistor.”).
`
`18
`
`
`
`
`
`d)
`“a memory module configured to receive and process
`commands, comprising a plurality of memory cells and
`circuitry, coupled to the first signal line and the second signal
`line,”
`
`
`
`Blood discloses this limitation. Ex. 1002-A at Claim 7. Blood discloses a
`
`plurality of memory cells. Ex. 1003, Blood at 2:23-39 (“It is to be understood that
`
`‘transmitter’ and ‘receiver’ mentioned in this specification are used as generic
`
`expressions to denote many diverse systems and subsystem components, such as
`
`teletypewriters, CRT display devices, memories, registers, central processing units
`
`and the like that function as a transmitter or receiver of digital signals.”) (emphasis
`
`added).
`
`
`
`Bruce additionally discloses a plurality of memory cells. Ex. 1002-A at
`
`Claim 1; Ex. 1005, Bruce at Figs 1 & 2.
`
`e)
`“for changing, during a period of time, an upper
`voltage level for a binary signal appearing on at least one of
`the first signal line and the second signal line in response to
`encountering at least one condition of the memory module
`during processing of a command,”
`
`
`
`Blood discloses a full-duplex transmission of a digital signal on a signal line.
`
`The digital signal on the line is a multi-level digital signal as shown in Blood Fig.
`
`3. The voltage signal on line 11 operates between a low voltage level and a high
`
`voltage level with intermediate voltage levels as seen as signal “O” of Fig. 3. An
`
`annotated version of Fig. 3 is provided below, showing a low voltage level in red, a
`
`high voltage level in blue, and an intermediate level in green:
`
`19
`
`
`
`
`
`
`
`
`
`A busy signal on the memory going low will cause the line 11 voltage to go
`
`to an intermediate voltage halfway between the high and low voltages on line 11
`
`when the processor side of the line is in the high state. Ex. 1002-A at Claim 7; Ex.
`
`1003, Blood at Fig. 3. When the processor side of the line is in the low state and
`
`the memory busy signal is in the low state, line 11 will be at the low voltage, which
`
`is less than the intermediate voltage. This condition occurs during the time the
`
`memory is in a “busy” state. “When both transmitters send, then the voltage level
`
`at the transmission line 11 shifts between three levels, as illustrated in Fig. 3; O.”
`
`Blood at 5:53-55.
`
`f)
`“the upper voltage level being a voltage level that is not
`exceeded by the binary signal appearing on the at least one of
`the first signal line and the second signal line,”
`
`
`
`As shown in the annotated Fig. 3 above, the upper voltage (blue line) is a
`
`voltage level that is not exceeded by the binary signal appearing on the signal line.
`
`20
`
`
`
`
`
`The upper voltage level shown in Blood Fig. 3 is the voltage level that corresponds
`
`to the binary signal level when both station A and B’s outputs are at binary High
`
`values.
`
`g)
`“the changing comprising switching the upper voltage
`level from a first voltage to a second voltage for indicating an
`occurrence of the at least one condition by the memory
`module”
`
`
`
`The intermediate voltage level shown (the green line in the annotated figure)
`
`is the voltage level corresponding to the memory module asserting a status
`
`condition. This intermediate voltage is a second voltage.
`
`h)
`“the first voltage being a voltage at which the memory
`module is powered and the second voltage being different
`from the first voltage,”
`
`
`
`The driver circuitry in Blood Fig. 4 is powered by VCC and VEE. The
`
`supply voltages for the circuit were 0 volts for VCC and -5.2 volts for VEE. Ex.
`
`1003, Blood at 6:3-4. Blood Fig. 3, line O shows the high level is 0 volts, which is
`
`equal to VCC. Therefore, Blood shows the first voltage being the same VCC voltage
`
`the system is powered by. Blood teaches that the second voltage is different from
`
`VCC.
`
`i)
` “wherein the at least one of the first signal line and the
`second signal line comprises the first signal line, the
`apparatus receives a clock signal on the first signal line, and
`the at least one condition comprises a busy status condition,”
`
`
`
`It is well-known for a device to send a busy conditi