United States Patent (19)
`Bailey et al.
`
`(54) ASYNCHRONOUSTRANSFER MODE
`ADAPTER FOR DESKTOPAPPLICATIONS
`
`75) Inventors: Chase B. Bailey, Highland Village;
`Klaus S. Fosmark, Dallas; Kenneth A.
`Laufenberger, Carrollton; William A.
`Perry, Carrollton; Kevin S. Dibble,
`Carrollton, all of Tex.
`73 Assignee: Efficient Networks, Inc., Dallas, Tex.
`
`21)
`22
`51
`(52.
`
`58)
`
`56)
`
`Appl. No.: 304,349
`Fed:
`Sep. 12, 1994
`Int. Cl. ....................... H04L 12/48; H04L 12/56
`U.S. Cl. .......................... 370/60.1; 370/79; 370/94.2;
`370/110.1
`Field of Search .................................. 370/60, 13, 79,
`370/17, 91, 85.1, 85.13, 60.1, 61, 58.1,
`58.2, 67, 85.14, 94.1, 94.2, 110.1; 395/200,
`325, 425, 500, 725, 800
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,231,631
`5,280,476
`5,311,509
`5,381,411
`
`7/1993 Buhrke et al. ............................ 370/60
`1/1994 Kojima et al. .......
`... 370/60.1
`5/1994 Heddes et al. ............................ 370/60
`1/1995 Ohno et al. ............................... 370/79
`OTHER PUBLICATIONS
`Daniel Minoli and Michael Vitella, "ATM Cell Relay Service
`for Corporate Environments,” New York: McGraw-Hill,
`Inc., 1994.
`
`||||||III
`USOO5548587A
`5,548,587
`Patent Number:
`Aug. 20, 1996
`Date of Patent:
`
`11)
`45
`
`Primary Examiner Alpus H. Hsu
`Assistant Examiner-Ricky Q. Ngo
`Attorney, Agent, or Firm-Baker & Botts, L.L.P.
`
`ABSTRACT
`(57)
`An ATM adapter for desktop applications includes an
`adapter for interfacing an ATM network. The adapter
`includes an ATM application specific integrated circuit
`(ASIC). The ATM ASIC may interface with a data bus such
`as an SBus using a host interface circuit. The host interface
`circuit includes a bus interface, a DMA controller and a
`slave access controller. The DMA controller controls DMA
`operations within the ATM ASIC and associates with a RAM
`interface arbiter. The slave access controller controls opera
`tion of an interrupt circuit that goes to the SBus as well as
`a statistics circuit. The RAM interface arbiter arbitrates
`communication between the DMA controller, the slave
`access control circuit, a segmentation engine, and a reas
`sembly engine. The RAM interface arbiter communicates
`with the RAM bus to a RAM associated with an adapter. The
`segmentation engine segments data into ATM format for
`transfer through a physical interface circuit. The physical
`interface circuit also receives formatted ATM information
`and sends that information to the reassembly engine. The
`reassembly engine reassembles the ATM data and transmits
`it through the RAM interface/arbiter circuit to the RAM bus.
`From the RAM bus, data may pass again through the RAM
`interface/arbiter to the DMA controller and onto the SBus
`through the host bus interface.
`
`42 Claims, 27 Drawing Sheets
`
`
`
`
`
`RAM BUS
`
`100
`CLOCK NPUT ?
`
`is
`
`is a
`
`a w up
`
`to its
`
`80 - an
`
`RAM
`INTERFACE/
`ARBER
`
`128
`
`CLOCK
`GENERATOR
`
`126
`
`SEGMENTATION
`ENGINE
`
`PHY
`INTERFACE
`
`
`
`
`
`
`
`
`
`104 HOST INTERFACE 198
`DMA
`ER CONTROLL
`
`
`
`BUS
`NTERFACE
`
`102
`
`SLAVE
`ACCESS
`CONTROL
`
`18
`
`INTEL EX. 1237.001
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 1 of 27
`
`5,548,587
`
`"
`
`End Stotion A
`(e.g., premises ATM switch)
`
`
`
`Upper loyers
`(e.g., TCP/IP or
`equivalent)
`
`
`
`End Station B
`(e.g., workstation/peripherol,
`permises ATM switch, or BISDN switch)
`Upper loyers
`(e.g., TCP/IP or
`equivalent)
`
`
`
`32
`
`18
`Peer-to-peer
`protocol
`
`50
`
`ATM layer
`
`
`
`28
`
`20
`Peer-to-peer
`
`wo
`
`protocol
`
`Peer-to-peer
`protocol
`
`46
`
`
`
`
`
`AALloyer
`
`M. MM D Dr. OX
`
`Message ID
`a
`multiplexing
`Segmentation
`Reassembly
`Reassembly error
`detection
`Cell multiplexing ATM layer
`Cell reloying
`Interface
`identification
`HEC generation
`HEC verification
`
`Line E.
`cop/
`Bit timing
`Physical medium
`
`
`
`interface
`
`
`
`Physical loyer v 5 1/24
`Physicol layer
`54
`Transmission
`Pete Tronsmission
`convergence
`convergence
`Physicol medium
`Physical medium
`dependent
`dependent
`
`
`
`
`
`
`
`
`
`26
`
`
`
`
`
`wo
`
`O Fiber, twisted-pair (premises only)
`
`o
`
`16
`
`FIC. 1
`
`INTEL EX. 1237.002
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 2 of 27
`
`5,548,587
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`80
`
`A
`
`/
`
`82
`Customer site
`
`HOST
`(e.g.,
`supercomputer)
`
`76
`
`74
`
`/
`
`/
`
`NY
`
`78
`Interface 1 ft.
`
`X t
`/y: 52
`Zé is
`
`
`
`
`
`66
`
`
`
`64
`ATM Switch
`
`60
`
`
`
`Interface
`
`86
`
`92
`
`Non-ATM
`WAN
`
`
`
`
`
`
`
`Peripherol
`(3. 2.5
`color printer
`
`/
`
`/
`
`84 A Interface 3
`
`ATM/BISDN
`public WAN
`
`
`
`88
`
`INTEL EX. 1237.003
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 3 of 27
`
`5,548,587
`
`FIG. 3
`
`
`
`R".
`
`
`
`
`
`
`
`112
`
`RAM
`INTERFACE/
`ARBER
`
`10
`
`HOST INTERFACE 108
`
`SBUS
`
`BUS
`INTERFACE
`
`
`
`
`
`
`
`
`
`SLAVE
`ACCESS
`CONTROL
`
`REASSEMBLY
`ENGINE
`
`118
`
`
`
`
`
`
`
`3 - 1
`
`7
`
`5
`
`FIG. 4
`
`MOTHERD
`CONTI
`
`CONSUN
`
`CONW6
`
`DAUGHTER ID
`
`Internal pull-up
`Mother boord ID code.
`When pull-up: SABRE compatible controller interface.
`When pull-down: normal controller interface.
`When pull-up: Asynchronous SUN interface.
`When pull-down: UTOPIA (see bit 5).
`When pull-up: UTOPIA interface.
`When pull-down: Non pipelined UTOPIA interface.
`Note: Must be pulled down when CONSUNl is
`pulled high.
`Daughter board ID code.
`
`
`
`
`
`
`
`
`
`INTEL EX. 1237.004
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 4 of 27
`
`5,548,587
`
`Register 0x00 (oddress 0x00): Midwoy Reset/ID Register (RESIDMCON)
`
`3-28
`
`27-11 -
`10-8
`R
`7
`
`x
`-
`
`5
`
`-
`MOTHER ID
`CONT
`
`CONSUN
`
`CONW6
`
`4-0
`
`
`
`DAUGHTER ID
`-
`R
`|| RESET
`
`
`
`
`
`
`
`
`
`When read returns Midway version
`number. This is version 0.
`Not used, undefined when reod.
`Mother boord ID code.
`O: Normal controller /f
`1: Reserved
`O: UTOPIA /f (see bit 5).
`1: Async. SUN i?f.
`O: Non pipelined UTOPIA /f
`1: UTOPIA /f
`(Must be 0 when bit 6 is 1.)
`Daughter board ID code.
`When written, the Midway is reset,
`all registers loaded with defaults.
`(The content of the doto bus is
`ignored by the Midwoy).
`
`
`
`FIG. 6
`
`INTEL EX. 1237.005
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet S of 27
`
`5,548,587
`
`Register 0x01 and 0x02 (address 0x04 and 0x08): Interrupt Stotus Acknowledge (ISA)
`and Interrupt Stotus (IS) Registers
`Default
`x
`
`-
`TXCOMPLETE 7
`
`TXCOMPLETE 6
`
`TX COMPLETE-5
`TX-COMPLETE_4
`
`TX COMPLETE-5
`
`TX COMPLETE 2
`
`TX COMPLETE.1
`
`TX COMPLETEO
`
`TXDMA OVF
`
`31-17 -
`16
`
`
`
`
`
`
`
`
`
`15
`
`4.
`13
`
`12
`
`11
`
`7
`
`5
`
`4.
`
`3
`
`2
`
`1
`
`X
`
`
`
`
`
`
`
`Not used, undefined when read.
`Interrupt indicating that channel 7
`completed a PDU transmission.
`Interrupt indicating that channel 6
`completed O PDU transmission.
`Interrupt indicating that channel 5
`completed a PDU transmission.
`interrupt indicating that channel 4
`completed a PDU transmission.
`Interrupt indicating that channel 3
`completed a PDU transmission.
`Interrupt indicoting that channel 2
`completed a PDU transmission.
`interrupt indicoting thot chonnel 1
`completed a PDU transmission.
`Interrupt indicating that chonnel O
`completed o PDU transmission.
`Interrupt indicating that the DMA from host
`memory to adopter caused on overflow.
`TX IDEN MISMTCH Interrupt indicating that the Segmentation
`Engine found a mismatch in the iden field
`of a Segmentation buffer. RX ENABLE,
`TXENABLE, and DMA ENABLE ore cleared.
`Interrupt indicating that a DMA operation
`received an LERR acknowledgement.
`Interrupt indicoting that a DMA operation
`received on error acknowledgement.
`RX DMA COMPLETE Interrupt indicating that a DMA from
`adopter memory to host memory has
`been completed.
`TXDMA COMPLETE Interrupt indicating that a DMA
`transfer from host memory to
`adopter memory hos been completed.
`Interrupt indicating that something
`has been put in the Service list.
`Interrupt indicating that the SUNI
`chip has the interrupt pin low.
`Interrupt indicating overflow on either
`VC. Trash or Ovf Trash statistics counters.
`HIC. 6
`
`DMALERRACK
`
`DMAERRACK
`
`SERVICE
`
`SUNLINT
`
`STAT. OVFL
`
`INTEL EX. 1237.006
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 6 of 27
`
`5,548,587
`
`Register 0x03 (address 0x00): Interrupt Enable Register (IE)
`Defoult Nome
`Description
`
`Not used, undefined when read.
`-
`Enoble TXCOMPLETE 7 Interrupts.
`|ENTX COMPLETE 7
`Enable TX COMPLETE 6 interrupts.
`ENTXCOMPLETE.6
`Enable TXCOMPLETE-5 interrupts.
`ENTX COMPLETE-5
`Enable TX COMPLETE 4 Interrupts.
`ENTX COMPLETE 4
`Enable IX COMPLETE-3 interrupts.
`ENTX COMPLETE-5
`Enoble IX COMPLETE 2 interrupts.
`ENIX-COMPLETE2
`Enable TX COMPLETE 1 interrupts.
`ENTX COMPLETE
`Enable IX COMPLETE
`Interrupts.
`ENIX COMPLETEO
`Enable TxDMA OVFL interrupts.
`ENTxDMA OVFL
`ENTX IDEN MISMTCH Enoble TX IDEN MISMTCH interrupts.
`ENDMALERRACK
`Enoble DMALERRACK interrupts.
`ENDMAERRACK
`Enoble DMAERRACK interrupts.
`ENRX DMA COMPLETE Enable Rx DMA COMPLETE interrupts.
`ENTXDMA COMPLETE Enable TxDMA COMPLETE interrupts.
`ENSERVICE
`Enable SERVICE interrupts.
`EN SUNLINT
`| Enable SUNLINT interrupts.
`ENSTALOVFL
`Enable SIALOVFL interrupts.
`FIC 7
`
`
`
`
`
`
`
`
`
`
`
`
`
`x
`31-17 -
`16
`R/W 0
`15
`R/W 0
`14
`R/W 0
`13
`R/W 0
`12
`R/W TO
`11
`R/W 0
`10
`R/W 0
`9
`R/W 0
`8
`R/W 0
`7
`R/W 0
`6
`R/W 0
`5
`R/W 0
`4
`R/W 0
`3
`R/W 0
`2
`R/wo
`R/W 0
`O
`R/W 0
`
`
`
`INTEL EX. 1237.007
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 7 of 27
`
`5,548,587
`
`Register 0x04 (oddress 0x10): Master Control/Status Register (MCS)
`
`FIC. 8
`
`31-9 -
`R/W
`
`X
`
`-
`INT SELECT
`
`5
`
`R/W
`
`TX LOCK MODE
`
`R/W
`
`DMA, ENABLE
`
`
`
`
`
`
`
`TXENABLE
`
`2
`
`R/W
`
`RXENABLE
`
`R/W
`
`WAITMS
`
`1
`
`
`
`R/W
`
`WAIT 500US
`
`
`
`
`
`
`
`Not used, undefined when read.
`Select interrupt level:
`000: Interrupts disabled
`001 : NTREQng) used
`010: INTREQng2X used
`11 : NTREQng7) used
`When O: Segmentation "streaming
`mode" on overflow
`When 1: Segmentation locks on
`overflow.
`Enoble DMA operations.
`When redd:
`0: Disabled
`1: Enobled
`When written:
`0: Don't change
`1: Enable DMA operations
`Enable Segmentation Engine.
`When redd:
`O: Disabled
`1: Enobled
`When written:
`0: Don't change
`1: Enable Segmentation Engine
`Enable Reassembly Engine.
`When redd:
`O: Disobled
`1: Enobled
`When written:
`0: Don't change
`1: Enable Reassembly Engine
`Interrupts are disabled for 1 mS.
`When reod:
`O: Timer not running
`1: Timer running
`When written:
`O: Don't change
`1: Stort 1 mS timer
`interrupts are disabled for 0.5 ms.
`When redd:
`O: Timer not running
`1: Timer running
`When written:
`O: Don't change
`1: Stort 0.5ms timer
`
`
`
`INTEL EX. 1237.008
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 8 of 27
`
`5,548,587
`
`Register 0x05 (oddress 0x14): Statistics Register (STAT)
`Default
`
`3-16
`
`15-0
`
`VC Trash
`
`Ovf Trosh
`
`The count of trashed cells becouse
`of WC mode set to Trosh.
`The Count of troshed cells becouse
`of Overflow.
`FIC. 9
`
`Register 0x06 (oddress 0x18): Serwrite Register (SERV WRITE)
`
`31-10 -
`
`
`
`0x0
`
`Not used, 0 when read.
`-
`r Points to the next free position to
`be written when the next PDU is to
`be put in the Service list.
`FIC. 1 O
`
`
`
`
`
`Register 0x07 (oddress 0x10): DMA Address Register (DMA ADDR)
`Default
`
`31-0
`
`DMA ADDR
`
`The virtual Oddress used for DMA.
`Can be read by the host for debug
`ging purposes.
`FIC. 1 1
`
`Register 0x08 (address 0x20): DMAWr rx Register (DMA WR RX)
`
`
`
`-
`0x0
`31-9 -
`r DMAW rx
`
`Not used, 0 when read.
`Points to the next free position to
`be written when the host wants to
`enqueue another block for DMA
`from adapter to host memory.
`FIC. 12
`
`
`
`INTEL EX. 1237.009
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 9 of 27
`
`5,548,587
`
`Register 0x09 (oddress 0x24): DMARd rx Register (DMARD RX)
`
`31-9 -
`
`
`
`0x0
`
`-
`DMARd rx
`
`Not used, 0 when read.
`Points to the descriptor currently
`being processed or about to be pro
`cessed by the Midway.
`FIC. 13
`
`Register OxOA (address 0x28): DMAWr tx Register (DMAWR-TX)
`
`
`
`
`
`-
`0x0
`31-9 -
`r DMAWr tx
`
`Not used, 0 when read.
`Points to the next free position to
`be written when the host wonts to
`enqueue another block for DMA
`from host to adopter memory.
`FIC. 14
`
`Register 0x0B (address 0x20): DMARd tx Register (DMARD TX
`)
`(
`)
`
`
`
`
`
`DMARd tx
`
`Points to the descriptor currently
`being processed or about to be pro
`cessed by the Midwoy.
`FIC. 16
`
`INTEL EX. 1237.010
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 10 of 27
`
`5,548,587
`
`Register 0x00 - 0x0F. (Not used)
`Register (0x10+(4 + channel) (address 0x40+(0x10 k channel)):
`Transmit Place Registers (TX PLACE )
`
`31-14 -
`13-11 R/W
`
`x
`
`-
`Size
`
`Not used, undefined when read.
`8 different sizes Ore defined for
`Segmentotion queues:
`"OOO"-256,
`
`r
`
`"111"-32K times 32 bit.
`The (up to) 11 most significant bits
`of the Oddress location of the cor
`responding Segmentotion-queue in
`Odopter memory. The (up to) 7
`least significant bits of this field
`must be zero (determined by Size).
`FIG. 16
`
`
`
`chonnel) (address 0x44+(0x10 k channel)):
`Register (Ox11+(4
`Transmit ReadPtr Registers (TXRDPTR)
`
`
`
`
`
`
`
`-
`0x0
`31-15 -
`II -
`
`Not used, 0 when read.
`Points to the next 52 bit word to be
`transferred to the PHY. The (up to)
`7 most significant bits of this field
`will be zero (determined by Size).
`FIC. 1 7
`
`chonnel) (address 0x48+(0x10
`Register (Ox12+(4
`Transmit DescrStart Registers (TXDESCRSTART)
`
`channel)):
`
`
`
`
`
`
`
`-
`0x0
`31-15 -
`T DescrStort
`
`Not used, 0 when read.
`tion buffer (its descriptor) cur
`Points to the start of the Segmenta
`rently being DMAed into the
`Segmentation queue. (Bit 0 is
`olwoys 0). The (up to) 7 most sig
`nificant bits of this field will be
`zero (determined by Size).
`FIC. 18
`
`INTEL EX. 1237.011
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 11 of 27
`
`5,548,587
`
`RAM read/write access
`ADR/DATA
`WEn
`OEn/CEn
`
`FIC. 19
`
`150
`?
`
`X
`
`X
`\/ 20ns
`40
`\7
`
`FIC. 20
`PHY/Generic write access
`ADR/DATA
`WEn/S CSn/G-CSn
`
`40ns
`
`A sons A
`
`40ns
`
`PHY/Generic read access
`
`FIC. 21
`
`ADR
`
`OEn/SSCn/GCSn
`
`A
`
`40ns
`
`20s
`
`A
`
`40ns
`
`152
`?
`
`154
`?
`
`f
`X
`
`FIC 22
`(E)E)PROM write access
`X
`ADR/DAIA
`WE/ECSn
`
`A
`
`40ns
`
`Sons
`
`A
`
`40ns
`
`(E)E)PROM read access
`
`FIC. 23
`
`:
`
`OEn/E-CSn
`
`A
`
`40ns
`
`2005
`
`A
`
`4Ons
`
`INTEL EX. 1237.012
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 12 of 27
`
`5,548,587
`
`Absolute Maximum Ratings:
`Porometer
`
`Min
`
`FIC. 24.
`Mox
`Unit
`
`ture under bias:
`
`
`
`
`
`
`
`
`
`DC input current
`Lead temperature
`Junction temperature
`
`I-8
`
`8
`+300
`+150
`
`mA
`oC
`oC
`
`Recommended operating conditions:
`
`FIC. 26
`
`Ambient operating tempero-
`ture:
`
`-70
`
`OC
`
`
`
`
`
`+28
`Output high voltage (note 1)
`Output low voltage
`-10
`input leakage current
`DC output current (note 2) TO
`
`+0.4
`+10
`TO
`
`v
`v
`UA
`mA
`
`
`
`
`
`
`
`
`
`FIC. 26
`
`Access to
`
`ReOd
`
`Write
`
`Woit stotes
`Access time ot 25MHz
`
`Woit stotes
`Access time at 25 MHz
`
`
`
`
`
`
`
`
`
`PHY
`(E)E)PROM
`
`440-480ns 8-9
`
`120-200ns 0-2
`
`INTEL EX. 1237.013
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 13 of 27
`
`5,548,587
`
`Byte address seen from host
`0x3FFFFF
`(2M byte RAM)
`
`Ox27FFFF
`(512K byte RAM)
`Ox21FFFF
`(128K byte RAM)
`
`224
`
`Ox2O7000
`222
`0x206000
`220
`Ox2O5000
`218
`0x204000
`
`216
`
`
`
`228
`
`Word address in adapter RAM
`
`/200
`
`adopter
`RAM
`
`0x1FFFF
`226
`0x07FFF
`
`0x01C00
`
`OxO1800
`
`0x0.400
`
`0x0000
`
`0x00000
`
`segmentation
`Ond
`reassembly
`buffers
`
`service list
`(1K words)
`DMA transmit queue
`(1K words)
`DMA receive queue
`(1K words)
`
`
`
`WC toble
`(4k words)
`
`aaya Saya SavaSAAayaaaayaaayaasawa Nawaway A 214
`
`Ox2OOOOO
`1.69 Mbyte gap
`X
`in address space -->
`0x04FFFF
`212
`0x040000
`
`MIDWAY
`registers
`(16K words (64K bytes))
`externo
`registers
`(16K words (64K bytes)
`(undefined)
`when read)
`(16K words (64K bytes)
`(E)EPROM R/W
`(FCode)
`(16K words (64K bytes)
`(E)EPROM R
`(FCode)
`(16K words (64K bytes))
`
`
`
`FIC. 2 7
`
`206
`-- PHY chip registers
`(mopped in low
`order byte)
`
`EPROM is byte
`addressable only
`
`
`
`210
`0x030000
`208
`0x02OOOO
`
`204
`0x00000
`
`2O2
`bOSe Oddress
`of Odopter -> 0x000000
`
`INTEL EX. 1237.014
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 14 of 27
`
`5,548,587
`
`Possible Transmit Engine Block Diogram
`
`
`
`
`
`Chonnel O
`
`PCR
`Circuit
`
`240
`
`FIC. 28
`
`
`
`
`
`
`
`Segmentation
`
`250
`
`
`
`232
`
`254
`
`CRC Generotor
`
`
`
`Internol Doto Bus
`
`238
`
`
`
`
`
`
`
`Word to Byte
`
`256
`
`To PHY
`interface
`block
`
`
`
`262 264. 266
`
`268
`
`270
`
`identifier M Pr Rote Res
`(4)
`(1)(2) (6 bits)
`4.
`274
`273
`(18)
`
`(8)
`
`VC
`
`Cell count
`(11 bits)
`PT CLP
`
`256
`1
`
`258
`1
`Segmentation
`buffer descriptor
`
`/260
`
`Doto
`
`toti
`S
`egg
`AAL5
`
`PDU
`Troiler
`282/
`
`
`
`
`
`(8)
`
`284
`
`
`
`Length
`CP
`(16 bits)
`(8)
`(CRC (will be ignored by Midway)
`(32)
`FIC. 3O
`
`INTEL EX. 1237.015
`
`

`

`US. Patent
`
`Aug. 20, 1996
`
`Sheet 15 of 27
`
`5,548,587
`
`0mm
`
`x.
`
`
`
`caselxemceF1<zo
`
`measelmmm\mmm
`
`mmawzououm
`
`Fgenetoom
`
`ooneselmum
`
`6:80<29\wo—
`
`NEscoolmom
`
`been:
`
`.QBEOQ
`
`Sm._o::8
`
`5,32
`
`39:22N_o:cooxomm
`
`.8358
`
`.20__2E8
`
`5:2:
`
`teem:
`
`.9358
`
`.20._EE8
`
`_o:coolomm
`
`5,2:
`
`o8:801QO
`
`@952
`
`.3858
`
`Sm._o:c8
`
`€32:
`
`cozoEmEomm
`
`Exam
`
`cosoEoEamm
`
`5:5
`
`cozoEoEmmm
`
`Exam
`
`cozscmEomm
`
`Scam
`
`INTEL EX. 1237.016
`
`INTEL EX. 1237.016
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 16 of 27
`
`5,548,587
`
`262 264 266 268
`
`
`
`256
`270 1 25
`
`Identifier M Pr Rote Res
`
`Cell Count
`
`Segmentation
`
`Cell
`
`...
`
`280
`
`2
`
`Data 1
`Data5
`
`-
`
`- -
`
`- -
`
`a -a- - -
`
`to
`
`;
`
`Doto2
`Data6
`
`274
`
`WC
`
`PT CLP
`
`Doto3
`
`- ---------------------------------------
`
`:
`
`m -
`
`pre- -
`
`- -
`
`-------------------
`
`FIC. 31
`
`DMA Transmit queue format
`
`
`
`260'
`
`1?
`
`Doto
`
`Segmentation
`buffer for
`non-AAL5
`
`DMA
`Descriptor
`
`Chon End
`Count
`(3)
`(1)
`(16 bits) (7)
`Host Oddress
`(32 bits)
`
`''
`(4)
`
`(1)
`
`Count:=0.(shitlood)
`Chon:=0.7
`End:={True="1", False="O"
`Type=JK="0011", Byte="0001",
`HWord="0010", Word="0000",
`2W="O111", 4W="0100",
`8W="0101", 16W="011 0",
`2WM="1111", 4WM="1100",
`8WM="1101", 16WM="1110":
`Host address:=0.(a lot)
`FIG. 33
`
`INTEL EX. 1237.017
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 17 of 27
`
`5,548,587
`
`FIC. 32
`
`Field Nome
`Location
`
`ReddPtr
`
`DescrStort
`
`CRC
`
`CellCount
`
`ATM header
`
`
`
`
`
`14
`
`R/W
`
`32
`
`11
`
`14
`
`R/W
`
`R/W
`
`R/W
`
`- || ||
`
`Rote Resolution
`
`
`
`II
`
`R/W
`
`15
`
`Segmentation Control block fields for channel 0-7
`Size
`Host
`Midway
`(bits) Access Access Description
`11
`R/W
`The (up to) 11 most significant bits of the
`address location of the corresponding Seg
`mentation queue in adapter memory. The Size
`field determines the number of bits in the
`location field used by the Midway to build the
`19 bit addres (see APPENDIX E:LOCATION/SIZE
`PARAMETERS). The (up to) 7 leost significant
`bits of this field must be zero (determined
`by Size).
`8 different sizes are defined for Segmentation
`queues: 256, 512, 1 K, 2K, 4K, 8K, 16K, and
`32K times 32 bit (i.e. from 1 K to 128K bytes).
`When 256 is selected, all bits of Location ore
`used. When 32K is selected, only the 4 most sig
`nificant bits of Location ore used (see APPENDIX
`E: LOCATION/SIZE PARAMETERS).
`Points to the next 52 bit word to be seg
`mented. When waiting to transmit a PDU,
`ReadPtr is compared with DescrStort. If
`different, Midway starts segmentation. The (up
`to) 7 most significant bits of this field ore
`zero (determined by Size).
`Points to the start of the Segmentation buffer
`(its descriptor) currently being DMAed into the
`Segmentation queue. This pointer is Odvanced
`when the whole PDU has been DMAed to Odapter
`memory. The (up to) 7 most significant bits of
`this field are zero (determined by Size).
`Contoins the tempoary CRC volue being calcu
`lated for the PDU currently being segmented.
`Contains the tempoory cell count for the PDU
`currently being segmented. Loaded from the
`segmentation queue, and counted down for
`each segmented cell.
`Cell header for the current PDU segmentation
`(VCI, PT), and CLP). Loaded from the
`segmentation queue.
`Prescole value for the PCR rote for the current
`PDU segmentation. Loaded from the segmen
`totion queue.
`Resolution volue for the PCR rote for the
`current PDU segmentotion. Loaded from the
`Segmentotion queue.
`
`INTEL EX. 1237.018
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 18 of 27
`
`5,548,587
`
`Pointers to the DMA Transmit queue
`Host
`Midway
`Size
`Field Name (bits) Access Access Description
`DMAWr tx
`R/W
`Points to the next free position to be written
`when the host wants to enqueue another block
`for DMA. The host is required to compore
`DMAWr tx and DMARd tx before a write operation
`to avoid overflows.
`Points to the descriptor currently being processed
`or about to be processed by the Midwoy. Midway
`compores DMAWr tx with DMARd tx to ovoid
`underflows.
`HIC. 34
`
`DMARd tx
`
`238
`
`Internol realister bus
`2
`
`316
`
`240
`f
`Peok Cell Rote Circuit
`
`314
`
`
`
`Rote Resolution
`
`328
`
`25MHz
`320
`
`C
`
`PresColer
`
`Counter
`
`C
`
`TC
`
`318
`
`322
`
`FIC. 36
`
`
`
`350
`
`334
`
`232
`
`INTEL EX. 1237.019
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 19 of 27
`
`5,548,587
`
`PCR Rotes
`PresCole
`Divisor
`
`Pr
`
`Rote
`Resolution
`
`FIC. 36
`
`PCR rate bits/sec) PCR rate cells/sec)
`Full speed
`Full speed
`147.2 Mb/s
`347222.2 cells/sec
`139.5 Mb/s
`328947.4 cells/sec
`42.1 Mb/s
`99206.3 cells/sec
`41.4 Mb/s
`97656.2 cells/sec
`Full speed
`Full speed
`132.5 Mb/s
`312500 cells/sec
`110.4 Mb/s
`260416.7 cells/sec
`10.5 Mb/s
`24801.6
`10.4 Mb/s
`24414.1 cells/sec
`195312.5 cells/sec
`97656.5 cells/sec
`3100.2 cells/sec
`3051.8 cells/sec
`12207.0 cells/sec
`6103.5 cells/sec
`1938 cells/sec
`190.7 cells/sec
`
`
`
`
`
`
`
`"101"-5
`"110"-6
`"111"-7
`
`32KB
`
`128KB
`
`Ocotiong 10-5) COncotenoted with Offset{12-0)
`LOCotion< 10-6) concotenoted with Offset {13-0)
`LOCotion<10-7) concotenoted with Offset{14-0X
`FIC. 37
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL EX. 1237.020
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 20 of 27
`
`5,548,587
`
`Location/Size
`
`
`
`Location
`
`
`
`
`
`19 bit Oddress
`
`
`
`
`
`
`
`544
`
`allellallallalo
`IIIllalellalo
`
`7
`
`
`
`FI G. 38
`
`7 6 5 4 3 2 1 0-- Size determines which
`bits ore controlled from Locotion
`
`
`
`Reassembly Doto Structures
`
`DMA Receive queue
`
`INTEL EX. 1237.021
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 21 of 27
`
`5,548,587
`
`370 372
`
`374
`
`t
`WC
`Descriptor
`
`
`
`
`
`
`
`
`
`390
`
`376
`WC table
`31
`Modes PT Modex LOCotion
`Size
`(2 bits)
`(1 bit)
`(11 bits) (3 bits)
`382
`DescrStart
`386
`(15 bits)
`584
`Stotek
`WritePt
`(Sits)(3)
`(SS) 392
`CRC Colc
`(32 bits) 594 596
`400
`
`352
`378 f 380
`
`in Service
`(14)
`*(1 bit)
`ReOdPt
`(15 bits
`388
`)
`CelCount
`SS 398
`
`(): Yeti. OO", AAL5="10", gas-or
`PT Mode:=Trash="O", Preserve="1"
`Size:={256="000",512="001"...32K="111"
`In Service:=True="1", Folse="O"
`State:=Trashing="11", Reassembling="01", Idle="00":
`
`HIC. 4O
`
`568
`
`416
`406 408 410
`Reassembly buffer
`31
`
`418 42 O
`
`O
`
`(7)
`
`
`
`(1)
`
`(3)(1) err(1) (11 bits)
`
`descriptor
`
`S.Sasir
`
`*
`
`buffer
`for AAL5
`
`Reassembly------------------------------- A
`
`d.
`
`456
`
`f
`Dato
`
`424
`
`
`
`(Received
`CPI)
`
`Iden:="0011011"
`T:=True="1", False="O"
`CRC err:=Truce="1", False="O"
`
`FIC 41
`
`INTEL EX. 1237.022
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 22 of 27
`
`5,548,587
`
`406
`
`
`
`31
`
`46
`
`O
`
`(7)
`
`4.38
`
`(1)
`
`(12 bits)
`
`(12)
`CellHeOder
`(32)
`Data4
`Doto3
`;
`Doto2
`;
`Data 1
`ReOSSembly--------------------------- -------------- --------------
`E. Doto5
`Doto.6
`
`368'
`p1.
`
`434
`f
`buffer
`descriptor
`
`-436
`
`a
`
`- - - - - - a m F-------------------------------------
`
`- as m -a - - - - - - - - - - - - - - - - - - - - - ------
`
`Doto
`
`
`
`
`
`
`
`rro - - - - - - as man-e- - W - - - - m an arm or won - - --- - - - - a
`
`were no or i-II
`
`FIC. 42
`
`440
`1.
`
`448 Service-list format
`
`
`
`
`
`FIC 43
`
`
`
`442
`Y
`(ServRead)
`
`
`
`Serwrite
`1
`444
`
`
`
`
`
`Pointers to the Service list
`Midway
`Host
`Size
`Field Nome (bits) Access Access Description
`Word offset that points to the next free position
`to be written when the next PDU is to be put
`in the list.
`FIC 44
`
`- I
`
`INTEL EX. 1237.023
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 23 of 27
`
`5,548,587
`
`DMA Receive queue format
`
`450
`
`Count:=0.(shitlood)
`VC:=0.1023
`End:=True="1", Folse="0":
`Type:=JK="0011", Word=0000",
`2W-"O 111", 4W="0100",
`8W="0101", 16W="011 0",
`2WM="1111", 4WM="1100"
`8WM="1101", 16WM-110
`y
`-
`Host Oddress:=0.(a lot)
`
`452
`
`DMA
`Descriptor
`1
`356
`
`Count
`WCI
`End
`Type
`(16 bits) cells local
`Host-Oddress
`(32 bits)
`
`FIC. 46
`
`
`
`
`
`
`
`
`
`
`
`Pointers to the DMA Receive queue
`Midwoy
`Host
`Size
`Field Nome (bits) Access. Access Description
`Word pointer to the next free position to be
`written when the host wants to enqueue another
`block for DMA. THe host is required to compare
`DMAWr rx and DMARd rx before a write operation
`to Ovoid overflows.
`Word pointer to the descriptor currently being
`processed or about to be processed by the
`Midway. Midway compares DMAWrrx with
`DMARd rx to ovoid underflows.
`FIC 46
`
`DMARdrx
`
`R/W
`
`INTEL EX. 1237.024
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 24 of 27
`
`5,548,587
`
`O
`
`Y
`
`Z f7 'f)I, H.
`
`
`
`INTEL EX. 1237.025
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 25 of 27
`
`5,548,587
`
`Host Interfoce Pins
`
`ACKC2:0>
`98.96,95
`I/O
`so I
`
`LERRn
`
`110
`
`CLK
`BGn
`
`|
`
`ASn
`
`78
`111
`
`"
`|
`
`45
`
`46
`
`D{31:OX
`
`INTREOng1:x
`
`24,27-31,35-
`;
`59,57-54,48,47
`90,84,75,71,
`64,58,52
`
`SZ<2:0>
`
`102.99,97
`
`scan-in-2 in scan mode)
`160pF SBUS bus request signal
`
`SBUS Address Strobe signal
`
`I/O
`
`160pF SBUS doto lines
`(Data output in RAM test mode)
`
`Interrupt requests
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Lood
`160pf SBUS Transfer acknowledgment. Input
`when master, Output when slave.
`(or<2:0> for in RAM test mode)
`SBUS Lote doto error. ...
`|| SBUs clock (16-25 MHz)
`-
`"
`SBUS bus grant signal
`| "It's
`
`SELn
`PAC21:2)
`
`
`
`READ
`
`RESEin
`
`122,118,115,
`114,109-105,
`94-92,87-85,
`83-80
`
`
`
`vo O
`
`160pf SBUS Transfer Size. Input
`when slave, Output when master.
`(ow<2:0> for in RAM test mode)
`SBUS Slove Select
`SBUS Physical Address.
`(PAK21> determines RAM or
`scan in Scon mode)
`SBUS Transfer Direction. Input
`when slave, Output when master.
`
`16OpF
`
`FIG. 48
`
`INTEL EX. 1237.026
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 26 of 27
`
`5,548,587
`
`Drive
`. . .
`t .
`EPROM chip select
`10pF
`|| 10pf
`Ceneral purpose chip select
`pu
`Interrupt request from phy chip
`(Scon-in-1 in scan mode)
`Address lines 18-0
`
`70pF
`
`RAM, EPROM, SUN Interface Pins
`
`its
`ECSn
`GCSn
`SINTn
`
`e
`145
`146
`13
`
`i
`|| 0
`
`ADR<18:0> 23-20, 16-127,
`6,186,187,189,
`190,192,193,
`198,199
`DATA<31:0> 119-121, 123-
`127, 130, 132
`134,138-143,
`150-155, 170
`172,175-179
`
`
`
`
`
`
`
`CEng 1:4)
`
`OEn
`scSn
`wEn
`
`113
`191
`188
`
`Miscelloneous Pins
`Pin Name Pin Number
`SMn
`O3
`
`OSCin
`
`183
`
`
`
`
`
`
`
`
`Doto lines 31-0
`(Data input in RAM test mode)
`
`10pF
`
`RAM chip selects. CEng 12 Octive
`for DATAK31:24),...,
`CEng4x Octive for DATAX7:0>.
`output Enable
`40pF
`SUN chip select (sel in T mode)
`10pf
`write Enable (R/W in T mode)
`50pF
`FIG. 49
`
`0
`0
`O
`
`Direction Drive
`
`Description
`Scon Mode control siqnol
`(low during SCOn tes
`Oscillotor input pin
`(master clock input).
`(20 pins) +5 volt D.C. power
`
`VOD
`
`WSS
`
`
`
`
`
`
`
`3,18,26,33,50,66,77,89,101,
`104,117,129,136,148,162,
`174,181,184, 195,208
`2,17,19,25,32,34,49,5153,65,
`67,76,79,88,100,116,128,
`135,137,147,149,157,161,
`173, 180,182,185,194,197
`FIC, 61
`
`(29 pins)
`
`
`
`
`
`INTEL EX. 1237.027
`
`

`

`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 27 of 27
`
`5,548,587
`
`PHY interfoce Pins
`
`RTCLK
`
`96
`
`RDAT<7:0> 156,158-160,
`163-166
`
`EMPTYn
`
`RENBn
`
`169
`
`RSOC
`
`167
`
`TDAT<7:0> 54,1207-203
`
`
`
`
`
`TENBn
`
`200
`
`FULLn
`
`2O1
`
`TSOC
`
`202
`
`
`
`
`
`
`
`30pF Transfer/synchronization clock for
`synchronizing transfers in both directions
`Received cell data from the PHY chip.
`RDAT<7> is the MSB
`(RDAT<0> is scan-in-3 in scan mode)
`(RDATK1> is scan-in-4 in scan mode)
`(RDAT<2> is scan-in-5 in scan mode)
`When asserted, Midway will assume
`thot RDAT is not void doto.
`When in SUNl mode, this pin is RCA.
`(Scan Enable (inv) in scan mode)
`15pF Asserted to indicate that RDAT and
`RSOC will read by Midway. When in
`SUN) mode, this pin is RRDB.
`When Osserted, RDAT Ossumed to
`contain the first byte of a cell.
`15pF Transmit cell doto. TDAT7 is the MSB.
`TDATKO) is scon-Out-3 in Scon mode
`TDAT< 1 > is SCOn-out-4 in Scan mode
`TDATK2> is scan-out-5 in scan mode)
`15pF Asserted during cycles when TDAT
`contoins void cell doto. When in
`SUN) mode, this pin is TWRB.
`When Osserted, Midway will stop writing
`bytes to the phy chip. When in
`SUN) mode, this pin is TCA.
`15pF Asserted when TDAT contains
`the first byte of the cell.
`FIG. 6O
`
`
`
`INTEL EX. 1237.028
`
`

`

`1.
`ASYNCHRONOUSTRANSFER MODE
`ADAPTER FOR DESKTOP APPLICATIONS
`
`5,548,587
`
`2
`cation traffic (voice, data, video, and image) is encapsulated
`in 53-byte cells for transport across the network. In contrast
`to traditional packet switching, no error processing occurs at
`the ATM layer, but is handled by the higher protocols in the
`attached DTE equipment. Therefore, ATM cells can be
`switched in hardware in gigabit speed with low delays.
`Because of the low latency and high throughput capabilities,
`ATM is the ideal technology to support these applications
`over the corporate network. It can support isochronous
`traffic, like voice and video, as well as bursty data, like local
`area internetworking, and traditional data, like SNA and
`X.25. The scalability of ATM makes it an attractive alter
`native for today's shared-media local area networks (LANs).
`Since only meaningful information, such as active speech
`or payload data, is encapsulated in ATM cells for transfer
`across the network, bandwidth resources are used efficiently.
`By not wasting bandwidth resources for idle flags and
`silence periods during conversation, networks can be
`designed to make better use of available wide area facilities.
`ATM networks can be designed for least cost, while main
`taining the quality of service (QoS) requirements of a wide
`variety of applications.
`The challenges that must be overcome to attain seamless
`network vision are substantial. First, there are differences
`surrounding ATM deployment in the local versus wide area
`networks. These result in varying implementations in local
`area network and wide area network products that must
`interoperate to provide total network solutions. Second,
`there is the requirement for multi-vendor interoperability.
`Third, there are economic aspects that must be considered
`when migrating to the seamless ATM network.
`Most of the focus in the local area network arena today
`has been put on pure data traffic. Voice and video are
`typically handled by specific communications equipment,
`completely separate from the local area network. Although
`multimedia is seen as one of the drivers of ATM to the
`desktop, current ATMLAN implementations are directed to
`the support of LAN data traffic only. On the other hand, a
`wide variety of traffic type traditionally has been supported
`over the wide area. To effectively integrate these traffic types
`with their specific performance criteria, ATM equipment
`must include sophisticated queuing, congestion, and routing
`algorithms.
`The seamless network providing desktop-to-desktop mul
`timedia networking is an exceedingly attractive solution that
`meets the high performance and flexibility required by
`future enterprise environments. To date, however, no
`method, system, or architecture having both an economi
`cally practical price and the desired level of performance
`exists that provides ATM network capabilities in the desktop
`environment.
`Consequently, there is the need for a system that provides
`ATM network capabilities in the desktop environment.
`There is a need for an ATM method and system that
`satisfactorily addresses the important considerations of local
`area and wide area network interoperability, multi-vendor
`interoperability, and economy in manufacture and imple
`mentation.
`There is, in essence, the need for a method and system that
`satisfactorily addresses requirements in terms of both price
`and performance in bringing ATM to the desktop.
`
`SUMMARY OF THE INVENTION
`Accordingly, the present invention provides an asynchro
`nous transfer mode (ATM) adapter for desktop applications
`
`TECHNICAL FIELD OF THE INVENTION
`The present invention is generally concerned with data
`communication systems and methods for transmitting and
`exchanging electronic data between two points and, more
`particularly, to an asynchronous transfer mode (ATM)
`adapter for providing ATM capability in a workstation or
`desktop environment.
`
`10
`
`BACKGROUND OF THE INVENTION
`In today's t