KINGSTON TECHNOLOGY COMPANY, INC. (Petitioner)
`v.
`POLARIS INNOVATIONS LTD. (Patent Owner)
`
`Oral Argument Demonstratives
`
`Case IPR2017-00116
`
`Patent 7,334,150
`
`1
`
`KINGSTON 1021
`Kingston v. Polaris
`IPR2017-00116
`
`
`v.
`POLARIS INNOVATIONS LTD. (Patent Owner)
`
`Oral Argument Demonstratives
`
`Case IPR2017-00116
`
`Patent 7,334,150
`
`1
`
`KINGSTON 1021
`Kingston v. Polaris
`IPR2017-00116
`
`
`
`Overview
`
`• Introduction to the Claimed Technology
`
`• The Claims are Obvious in View of Dodd
`
`• The Claims are Obvious in View of Lee
`
`2
`
`
`
`INTRODUCTION TO THE CLAIMED
`TECHNOLOGY
`
`INTRODUCTION TO THE CLAIMED
`
`TECHNOLOGY
`
`3
`
`
`
`The ’150 Patent is About A Registered Memory Module
`
`• DRAM Memory Chips 4
`• One Common Chip Packing 11 (including a Clock
`Regeneration Circuit 12 and a Register 13).
`
`‘150 Patent, Ex. 1001, Fig. 1
`
`4
`
`
`
`The ’150 Patent is About A Registered Memory Module
`
`• External Clock Signal 61 and Command/Address
`Signal 71 Received by Chip 11
`• Clock Signals 62 and Command/Address Signals 72
`generated by Clock Regen Circuit and Register
`
`‘150 Patent, Ex. 1001, Fig. 1
`
`5
`
`
`
`The ’150 Patent is About A Registered Memory Module
`
`‘150 Patent, Ex. 1001, Fig. 2, 4:56-62
`
`6
`
`
`
`Independent Claim 1
`
`Independent Claim 1
`
`1. A memoryr module. comprising;
`a plurality of memory chips arranged on the memory
`module;
`lines operable to supplyr an
`a plurality of bus signal
`incoming clock signal and incoming command and
`address signals to at least the memory chips;
`a clock signal regeneration circuit configured to generate
`a plurality of copies of the incoming clock signal and
`to supply the copies ofthe incoming clock signal to the
`memory chips; the copies of the incoming clock signal
`having a same frequency as the incoming clock signal;
`and
`
`a register circuit arrange on the memory module in a
`common chip packing with the clock regeneration
`circuit and configured to receive one of the copies of
`the incoming clock signal from the clock regeneration
`circuit; the register circuit being further configured to
`temporarily store the incoming command and address
`signals and to generate a plurality of copies of the
`incoming command and address signals and supply the
`copies of the incoming command and address signals to
`the memory chips; the copies of the incoming com-
`mend and address signals having a same frequency as
`the incoming command and address signals.
`
`Memory module haying chips
`
`-
`CIOCk and C/A 111168 “3 module
`
`-
`-
`-
`831116 fi'fiq. COPIES 0f incoming
`CIUCk signal 11) memory ChipS
`
`Register circuit that iS
`GunfigHI-Ed t0 IECEIVE 3- copy 0f
`incoming clock signal
`
`_
`Same freq 0013168 0f C/A
`'
`'
`Slgnals to memory ChlpS
`
`Ex. 1001
`
`7
`
`
`
`All Instituted Claims of ’150 Patent Are Obvious
`
`References
`
`Claims Obvious
`in Light of References
`
`Dodd and Dodd/Keeth
`
`1, 2, 3, 5, 6, and 8-11
`
`Lee and Lee/Keeth
`
`1, 2, 3, 5, 6, and 8-11
`
`PO Resp. at 3
`
`8
`
`
`
`DODD AND DODD/KEETH COMBINATIONS
`RENDER ALL INSTITUTED CLAIMS OBVIOUS
`
`DODD AND DODD/KEETH COMBINATIONS
`
`RENDER ALL INSTITUTED CLAIMS OBVIOUS
`
`9
`
`
`
`Dodd & Keeth
`
`Dodd, Ex. 1003
`
`Keeth, Ex. 1016
`
`Fig. 5
`
`1:25-32
`
`10
`
`
`
`Dodd Renders Claim 1 Obvious
`
`• Dodd discloses an ADDR/CMD Buffer 122 located on the Memory Module
`150
`
`Ex. 1003, Fig. 3
`
`11
`
`
`
`Dodd Renders Claim 1 Obvious
`
`Ex. 1001, Fig. 1
`
`Ex. 1003, Fig. 3
`
`12
`
`
`
`Dodd Renders Claim 1 Obvious
`
`Ex. 1003, Fig. 3
`
`Ex. 1003, 6:3-11
`
`13
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses “configured to temporarily store”
`
`•
`
`’150 Patent describes buffering C/A signals:
`
`• Dodd discloses the ADDR/CMD Buffer 122:
`
`Ex. 1001 at 4:57-58
`
`14
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses “configured to temporarily store”
`
`• There is no basis to differentiate Dodd based on the buffer 122.
`
`•
`
`’150 Patent describes temporary storage as “buffered.” Ex.
`1001 at 4:57-58
`
`• Dodd describes the ADDR/CMD buffer 122 as being “buffers
`or registers”:
`
`Ex. 1003, 2:65-67
`
`15
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses “configured to temporarily store”
`
`• Even if Dodd is held to be limited to the use of buffers based on
`latches, Dodd still discloses temporary storage:
`
`• “Holding” is temporary storage.
`
`• Dr. Subramanian testified that an “RDIMM that buffers control
`signals” would have “a storage location where it store the digital
`representation of the incoming signals.” Ex. 2018 at 23:2-14
`
`16
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses a Register Circuit that receives a same frequency
`copy of the clock signal.
`
`• Patent Owner alleges:
`
`• But Dodd explained that delay was a principal problem in the
`prior art:
`
`POR at 21
`
`Ex. 1003, at 1:57-62
`
`17
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses a Register Circuit that receives a same frequency
`copy of the clock signal.
`
`• Dodd’s Register is setup the same as the ’150 Patent:
`
`•
`
`In both, the register resides on a chip that receives (a) an
`external (incoming) clock, and (b) uses a clock regeneration
`circuit to generate the clocks for the C/A buffer and the memory
`chips.
`
`18
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses a Register Circuit that receives a same frequency
`copy of the clock signal.
`
`• Dodd explicitly states that
`
`Ex. 1003 at 6:7-11
`
`Ex. 1003 at 3:9-12
`
`19
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses a Register Circuit that receives a same frequency
`copy of the clock signal.
`
`• Dr. Subramanian testified:
`
`Ex. 1011 at ¶45
`
`20
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd discloses or renders obvious a central position
`
`21
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dr. Subramanian’s provides reasons why a POSITA would use a
`central position:
`
`Ex. 1011 at ¶58
`
`22
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd teaches an improved RDIMM
`
`• RDIMM stands for “Registered Dual Inline Memory Module”
`
`• Term is used twice in the specification and never defined.
`
`• No disclaimer of having data buffers & no “consisting of”
`language
`
`• Petitioner proposed “a Dual In-Line Memory Module that has
`circuitry to buffer control signals, addresses, or data.”
`
`• Board elected to not construe the term in the Institution
`Decision
`
`• Patent Owner did not argue a competing construction in its
`POR.
`
`23
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Dodd teaches an improved RDIMM
`
`• Dodd shows a DIMM module that uses a C/A register:
`
`Ex. 1003, 2:65-67
`
`Ex. 1011 at ¶62
`
`24
`
`
`
`LEE AND LEE/KEETH COMBINATIONS
`RENDER ALL INSTITUTED CLAIMS OBVIOUS
`
`LEE AND LEE/KEETH COMBINATIONS
`
`RENDER ALL INSTITUTED CLAIMS OBVIOUS
`
`25
`
`
`
`Lee
`
`Lee
`
`Lee, Ex. 1008
`
`Lee, Ex. 1008
`
`MEMORY MEMORY MEMORY
`DEVICE
`DEVICE
`DEVICE
`
`MEMORY MEMORY
`
`
`RCLK”)
`
`MEMORY
`
`um
`Ram)
`
`
`
`REGISTER I
`l
`
`
`' RCLK(0)
`
`|
`
`
`
`
`
`
`WCLK(8)
`
`RCLK(D)
`
`
`
`RCLK(1)RCLK(2)
`RCLK(6)
`RCLKG)
`RCLK(S)
`
`FIG. 4
`
`27
`
`t
`FIG. 4 illustrates in
`reater detail a memo
`subsystem
`2:, which asNH. m
`
`4illustratestheWCLKregenerationcircuit41asa(PLL)
`
`phase lock loop which provides the respective WCLK
`
` n a
`
`Ex. 1008 at 7:26-34
`slgna s
`.
`1tlon,t e
`. RCLK(8} are shown as coming off the bus
`.
`RCLKfll} .
`having been generated by the FIG. 3 RCLK regenerator
`circuit 43 connected to line 21.
`
`EX. 1008 at 7:26-34
`
`26
`
`
`
`Lee Renders Claim 1 Obvious
`
`Ex. 1008, Fig. 4
`
`Ex. 1011 at ¶80
`
`27
`
`
`
`Patent Owner’s Arguments Do Not Stand
`
`• Lee discloses a register circuit “configured to receive one of the copies
`of the incoming clock signal…”
`
`• Claim language is directed to the configuration of the “register
`circuit” rather than the operation of the “clock signal
`regeneration circuit.”
`
`• Claim language does not require the copy of the clock signal to
`“have the same frequency” unlike the claim language used for
`the memory chips and the command and address signals.
`
`28
`
`
`
`Patent Owner’s Arguments Do Not Stand
`
`• Lee discloses a register circuit “configured to receive one of the copies
`of the incoming clock signal…”
`
`Ex. 1011 at ¶77
`
`29
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`•
`
`It would be obvious to place Lee’s PLL and Register in a single package
`or common chip
`
`Ex. 1011 at ¶75
`
`30
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`•
`
`It would be obvious to place Lee’s PLL and Register in a single package
`or common chip
`
`Ex. 1011 at ¶76
`
`31
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`•
`
`It would be obvious to place Lee’s PLL and Register in a single package
`
`• Dr. Bernstein does not assert that Dr. Subramanian’s description
`of the industry trend consolidating circuits, but rather argues that
`the a common chip packaging was too technically difficult.
`
`• BUT, the ’150 Patent describes no technical solution or innovation
`that enables combining a PLL and a register in a single package –
`it simply declares that it should be done.
`
`• AND, the Dodd patent evidences that combining a PLL and a
`register into a single package was known in art before the ’150
`patent – making any results of the combination eminently
`predictable to a POSITA.
`
`• AND, Lee describes its DIMM as a memory device, which Polaris
`has argued means a single packaged chip. Reply at 17.
`
`32
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Lee discloses multiple copies of the Command and Address Signals
`
`Reply at 19
`
`33
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Lee renders obvious placing the common chip packing in a central
`location:
`
`• As well as obvious for all of the reasons described in regard to Dodd.
`
`34
`
`Ex. 1008
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• Lee discloses an RDIMM:
`
`• Lee does not describe data buffers and Patent Owner identifies no
`difference between Lee and an RDIMM other than Lee not being
`“commercial.”
`
`• No basis in law to argue that Lee must affirmatively state that it does
`not include unclaimed data buffers.
`
`35
`
`
`
`Patent Owner’s Arguments Cannot Stand
`
`• There is no legal precedent finding
`IPRs to be unconstitutional.
`
`36
`
`
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