(12)UK
`
`(19)GB (“)2
`
`(13)B
`
`(45) Date of publication:
`
`10.09.2003
`
`(54) '|'It|e oftheinvention: System comprising memory module
`
`(51)
`
`Int CI7: G11c 8/1811/408
`
`
`(21) Application No:
`0225250.0
`(72)
`|nventor(s):
`
`Dong-yang Lee
`
`
`
`(22) Date of Filing:
`
`Date Lodged:
`
`22.08.2001
`
`30.10.2002
`
`(30) Priority Data:
`(31) 00052377
`(31) 00079186
`
`(32) 05.09.2000
`(32) 20.12.2000
`
`(33) KB
`(33) KB
`
`(62) Divided from Application No
`0120457.7 under Section 15(4) of the Patents
`Act 1977
`
` Date A Publication:
`
`12.03.2003
`
`UK CL (Edition V):
`G4C C11408B C800T
`G4A AMX
`
`(56) Documents Cited:
`GB 2367400 A
`
`GB 2178204 A
`
`(58) Field of Search:
`As for published application 2379542 A viz:
`UK CL (Edition V) G4A, G4C
`INT CL7 G06F, G11c
`Other: Online: EPODOC, JAPIO, WPI
`updated as appropriate
`
`
`
`(73) Proprietor(s):
`Samsung Electronics Co., Ltd.
`(Incorporated in the Republic of Korea)
`Gone Away, Kyungki-do,
`Republic of Korea
`
`(74) Agent and/or Address for Service:
`Marks & Clerk
`57-60 Lincoln's Inn Fields, LONDON,
`WC2A 3LS, United Kingdom
`
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`SYSTEM COMPRISING MEMORY MODULE
`
`The present invention relates to a memory device and to a memory module and system,
`
`and more particularly, the present invention relates to a semiconductor memory device
`
`which generates internal clock signals and to a memory module and system having the
`same.
`
`The increasing demand for computer systems capable ofprocessing large amounts of
`
`data at high speeds has resulted in the continued development of highly efficient micro-
`
`controllers or central processing units (CPUs) which tend to operate at higher and
`higher system clock frequencies. The use of higher system clock frequencies requires,
`among other things, an increase in the data capacity and transmission speed of a data
`
`In other words, the memory must be configured to
`memory interfacing with the CPU.
`operate in synchronization with higher-frequency system clock signals.
`
`FIG.
`
`1 is a diagram illustrating a memory controller 110 and a memory module 120 of a
`
`CPU system board 100. The memory controller 110 transfers a clock signal CLK, an
`
`address signal ADDR, a command signal CMD and data DATA to the memory module
`120 through a CLOCK BUS line, an ADDRESS BUS line, a COMMAND BUS line
`
`and a DATA BUS, respectively. The memory module 120 includes a plurality of
`
`memory chips (e.g., 8 memory chips) 101, 102,..., 108 embedded therein, each of which
`
`is connected to the CLOCK BUS line, the ADDRESS BUS line, the COMMAND BUS
`
`line and the DATA BUS as shown.
`
`The clock signal CLK is supplied to the memory chips 101, 102,..., 108 to control the
`
`operation thereof. Also, in the case where the memory chips 10], l02,..., 108 are
`
`synchronous DRAM chips, the command signal CMD, the address signal ADDR and
`the data DATA are synchronized with edges of the clock signal CLK.
`
`14
`14
`
`

`
`As shown in FIG. 1, the data DATA is input to/output from the memory chips 101 ,
`
`102,..., 108 via the DATA BUS through independent multi-bit data lines connected to
`
`the respective memory chips 101, 102,..., 108. Thus, the load of each data line is one
`
`memory chip. On the contrary, the address signal ADDR and the command signal
`
`CMD are commonly supplied to the memory chips 101, 102, ..., 108. As such, the
`
`ADDRESS BUS and COMMAND BUS lines are each subjected to the combined load
`
`of all ofthe memory chips 101, 102, ..., 108.
`
`As suggested previously, high speed CPUs are attended by high frequency clock signals
`
`CLK. Generally, the data DATA of the DATA BUS may be operated at such high
`
`frequencies since the load of each data line is relatively small (one memory chip). On
`
`the other hand, relatively high multi-mernory chip loads of the ADDRESS BUS and
`
`COMMAND BUS lines can prevent high frequency operation of these lines. The loads
`
`of the ADDRESS BUS and COMMAND BUS lines can therefore limit the effective
`
`operating speed of the memory to less than the system clock speed.
`
`FIG. 2 is a block diagram of a conventional memory module 120. A plurality of bus
`
`lines connected to a microprocessor (not shown) or a memory controller (not shown),
`
`typically a clock bus, an address bus and a command bus, are arranged on a system
`
`board. The memory module 100 includes a plurality of memory chips 101, 102,..., 106,
`
`a phase locked loop (PLL) 107 and a register 108.
`
`The PLL 107 receives a clock signal CLK loaded on the clock bus line and generates a
`
`plurality of internal clock signals ICLKO, ICLK1 ,...lCLK6.
`
`It is assumed here that the
`
`plurality of internal clock signals ICLKO, ICLK1,...lCLK6 are ideal signals having the
`
`same slew rate and duty cycle without skew. Since the plurality of internal clock
`
`signals ICLKO, ICLK1,...ICLK6 are synchronized in phase with the clock signal CLK,
`
`they have the same frequency as that of the clock signal CLK. The internal clock signal
`
`ICLKO is supplied to the register 108, and the internal clock signals ICLK1, ICLK2,...,
`
`ICLK6 are supplied to the memory chips 101, 102,..., 106.
`
`In FIG. 2, one clock signal
`
`is connected to one memory chip. However, in actual applications, the number of
`
`corresponding memory chips for one clock signal may vary. The register 108 receives
`
`15
`15
`
`

`
`3
`
`the address signal ADDR and the command signal CMD in response to the intemal
`
`clock signal and transmits the received signals to the respective memory chips 101,
`102,..., 106.
`
`Since the memory module 120 receives only one clock signal CLK and generates a
`plurality of internal clock signals ICLKI, ICLK2,..., ICLK6, the frequencies of the
`
`internal clock signals lCLK1, ICLK2,..., ICLK6 increase as the frequency ofthe clock
`signal CLK increases in a high-perforrnance system. Since the memory chips 10],
`l02,..., 106, which receive the internal clock signals ICLK1, ICLK2,..., ICLK6 and
`
`operate responsive thereto, may be constructed of devices suitable for high—frequency
`operation, no problems arise from their operation. However, it is doubtful whether the
`
`register 108 can function to receive the address signal ADDR and the command signal
`CMD at a timing corresponding to the frequency ofthe internal clock signal ICLKO,
`that is, the high frequency clock signal CLK, and to then transmit the received signals to
`the memory chips 10], l02,..., 106, in synchronization with the same high frequency
`clock signal CLK. As such, the operating characteristics of the register 108 may also
`limit the effective operating speed of the memory to less than the system clock speed.
`
`It is an objective of the present invention to provide a semiconductor memory device
`which can utilize operable frequencies of an address signal and a command signal even
`if the frequency of a system clock signal is increased.
`
`It is another objective of the present invention to provide a system having a memory
`device and a memory module which can utilize a clock signal having a sufficiently low
`frequency which is suitable for the operation of a register even if the frequency of a
`system clock signal is increased.
`
`According to one aspect of the present invention, there is provided a system as set out in
`Claim 1. Preferred features of this aspect are set out in Claims 2 to 4.
`
`According to a second aspect of the present invention, there is provided a system as set
`out in Claim 5. Preferred features of this aspect are set out in Claims 6 to 8.
`
`16
`16
`
`

`
`According to a third aspect of the present invention, there is provided a system as set
`
`out in Claim 9. Preferred features ofthis aspect are set out in Claims 10 to 12.
`
`4
`
`The above and other objectives and advantages of the present invention will become
`
`more readily apparent from the detailed description that follows, with reference to the
`
`accompany drawings, in which:
`
`FIG. 1 depicts a conventional memory controller and a memory module of a CPU
`
`system board;
`
`FIG. 2 is a block diagram of a conventional memory module mounted on the system
`
`board shown in FIG. 1;
`
`FIG. 3 is a block diagram of a semiconductor memory device;
`
`FIG. 4 depicts a system board having a semiconductor memory device;
`
`FIG. 5 is a block diagram of the semiconductor memory device shown in FIG. 4;
`
`FIG. 6 is an operational timing diagram of the semiconductor memory devices shown in
`
`FIG. 3 and 5;
`
`FIG. 7 depicts a system including a memory module;
`
`FIG. 8 depicts a system including a memory module according to a first embodiment of
`
`the present invention;
`
`FIG. 9 depicts a system including a memory module;
`
`FIG. 10 depicts a system including a memory module according to a second
`
`embodiment of the present invention;
`
`FIG. 1 1 depicts a system including a memory module; and
`
`17
`17
`
`

`
`FIG. 12 depicts a system including a memory module.
`
`Preferred embodiments of the present invention will now be described in detail with
`
`reference to the accompanying drawings, in which like elements are denoted by like
`references numbers.
`
`FIG. 3 depicts a semiconductor memory device. A semiconductor memory device 101,
`
`which generally corresponds to one of memory chips included in a memory module
`
`(e.g., modulel20 of FIG. 1), includes a clock buffer 310, an address buffer 320, a
`
`command buffer 330, a data buffer 340 and a controller 350. The clock buffer 310
`
`receives a clock signal CLK (referred to herein as an "extemal clock signal") loaded on
`
`a CLOCK BUS, and generates internal clock signals CLK1 and CLK2. The relative
`
`frequencies of the first internal clock signal CLK1 and the second clock signal CLK2
`
`are determined by the clock buffer 310 in response to a control signal CTRL output
`
`from the controller 350. For example, the control signal CTRL may designate which of
`
`a rising or falling edge of the external clock signal CLK that the first internal clock
`
`signal CLK] is to be synchronized. The controller 350 may be constituted by a mode
`
`resister set (MRS), and the control signal CTRL may be set at a time of powering-up the
`
`semiconductor memory device 101 and/or upon cancellation of a power-down mode.
`
`The frequency of the first internal clock signal CLK] relative to the frequency of the
`
`second internal clock signal CLK2 may vary according to the control signal CTRL. The
`
`case where the frequency of the first internal clock signal CLK1 is lower than that of the
`
`second internal clock signal CLK2 will now be described. In this example, the
`
`frequency of the second internal clock signal CLK2 is substantially the same as that of
`
`the extemal clock signal CLK. As such, assuming that the frequency of the external
`
`clock signal CLK is 400 MHZ, then the second internal clock signal CLK2 also has a
`
`frequency of 400 MHz. The first internal clock signal CLK1 may, for example, have a
`
`frequency which is half or less that of the second internal clock signal CLK2. Thus,
`
`assuming again that the frequency of the second internal clock signal CLK2 is 400
`
`MHz, then the first internal clock signal CLK1 may have a frequency of 200 MHz or
`100 MHZ.
`
`18
`18
`
`

`
`The address buffer 320 receives the address signal ADDR at a timing of the first
`
`internal clock signal CLK1. Likewise, the command buffer 330 receives the command
`
`signal CMD at a timing ofthe first internal clock signal CLKI. On the other hand, the
`
`data buffer 340 inputs/outputs data DATA at a timing of the second internal clock
`
`signal CLK2.
`
`In operation, the semiconductor memory device 101 receives the high—frequency
`external clock signal CLK.
`In this arrangement, the second internal clock signal CLK2
`
`generated by the clock buffer 310 has the same frequency as the external clock signal
`CLK, e.g., 400 MHz. This means that the semiconductor memory device 101
`
`inputs/outputs data DATA in synchronization with the external clock signal CLK,
`which is the operating frequency of a memory controller or a microprocessor mounted
`
`on the system board.
`
`In contrast, the address signal ADDR and the command signal CMD are processed in
`synchronization with the first internal clock signal CLKI which has a lower frequency
`than that of the external clock signal CLK.
`In this manner, the high-frequency device
`limitations previously imposed by the loads of the ADDRESS BUS line and the
`
`COMMAND BUS line may be overcome, thus making the semiconductor memory
`device 101 well adapted to high-frequency operations.
`
`A data strobe signal STROBE may be applied to the data buffer 340 to control latching
`of the high-frequency data DATA.
`In this case, the data buffer 340 inputs/outputs data
`DATA in response to an edge of the strobe signal STROBE. In particular, a single data
`rate (SDR) dynamic random access memory (DRAM) inputs/outputs data at every
`rising or falling edge of the strobe signal STROBE. A double data rate (DDR) DRAM
`inputs/outputs data at both rising and falling edges of the strobe signal STROBE.
`
`FIG. 4 depicts a system board 400 having a semiconductor memory device. The system
`board 400 includes a memory controller 410 and a memory module 420 having a
`plurality of memory chips 401, 402,..., 408. The memory controller 410 generates a
`first clock signal CLKI, a second clock signal CLK2, an address signal ADDR, a
`
`19
`19
`
`

`
`7
`
`command signal CMD and a data signal DATA and transmits the generated signals to a
`
`CLOCK] BUS, a CLOCK2 BUS, an ADDRESS BUS, a COMMAND BUS and a
`
`DATA BUS. The frequency of the second clock signal CLK2 of this second
`
`arrangement is substantially the same as that of the external clock signal CLK of the
`
`first arrangement. Likewise, the frequency of the first clock signal CLK1 of this second
`
`arrangement generally corresponds to that of the first clock signal CLK1 of the first
`
`arrangement.
`
`Each ofthe memory chips 40], 402,..., 408 is connected to the CLOCKI BUS, the
`
`CLOCK2 BUS, the ADDRESS BUS, the COMMAND BUS and the DATA BUS, and
`
`receives the first clock signal CLK1, the second clock signal CLK2, the address signal
`ADDR, the command signal CMD and the data signal DATA.
`
`FIG. 5 illustrates an example of a memory chip 401 contained in the memory module
`
`420 of FIG. 4. The memory chip 401 includes an address buffer 520, a command buffer
`
`530 and a data buffer 540. The address buffer 520 receives the first clock signal CLK1
`
`and the address signal ADDR, and the command buffer 530 receives the first clock
`
`signal CLK1 and the command signal CMD. The data buffer 540 receives the second
`
`clock signal CLK2 and the data signal DATA.
`
`As with the first arrangement, the address signal ADDR and the command signal CMD
`
`are processed in synchronization with the first internal clock signal CLK1 which has a
`
`lower frequency than that of an external clock signal CLK (or second internal clock
`
`In this manner, the high-frequency device limitations previously
`signal CLK2).
`imposed by the loads of the ADDRESS BUS line and the COMMAND BUS line may
`be overcome.
`
`An operational timing diagram of the memory chips of the first and second
`
`arrangements is shown in FIG. 6. Generally, the period of the first internal clock signal
`CLK1 is preferably an integer multiple of a period of the external clock signal CLK.
`In
`this example, the frequency of the first internal clock signal CLK1 is half that of the
`
`external clock signal CLK (or the second internal clock signal CLK2). The address
`signal ADDR and the command signal CMD include setup and hold time margins
`
`20
`20
`
`

`
`8
`
`relative to the rising edge of the first internal clock signal CLK1. In the case of a single
`
`data rate (SDR) DRAM semiconductor memory device, the data is output through a
`
`data temiinal DQ at every rising or falling edge of the second internal clock signal
`
`CLK2 (which has the same frequency as the external clock signal CLK).
`
`In the case of
`
`a double data rate (DDR) DRAM semiconductor memory device, the data is output
`
`through a data terminal DQ at both the rising and falling edges of the second internal
`
`clock signal CLK2.
`
`In the case where the data buffer included in the memory chip of the first or second
`
`embodiment is connected to receive a data strobe signal STROBE, the data is
`
`input/output at both the rising and falling edges of the data strobe signal STROBE as
`
`shown in FIG. 6. This operation generally corresponds to that of the DDR DRAM.
`
`FIG. 7 depicts a memory module 700. The memory module 700 includes a plurality of
`
`memory chips 701 , 702,..., 706, and a register 710. The register 710 is connected to
`
`receive a first clock signal CLK1, an address signal ADDR and a command signal CMD
`
`loaded on a system board. The register 710 stores the address signal ADDR and the
`
`command signal CMD at a timing of the first clock signal CLK1, and transfers the same
`
`to the memory chips 701, 702,..., 706. In this arrangement, the address signal ADDR
`
`and the command signal CMD output from the register 710 are transmitted in one
`
`direction (left-to-right in FIG. 7) across the memory module 700 to the memory chips
`
`701, 702,..., 706.
`
`The memory chips 70], 702,..., 706 are connected to received the second clock signal
`
`CLK2 loaded on the system board and the address signal ADDR and the command
`
`signal CMD output from the register 71 O. The second clock signal CLK2 has a higher
`
`frequency than the first clock signal CLK1. The first clock signal CLK1, the address
`
`signal ADDR and the command signal CMD may be directly supplied to the memory
`
`chips 701, 702,..., 706, i.e., without passing through the register 710 in the memory
`
`module 700. Here, the first clock signal CLK1 serves to drive an address buffer and a
`
`command buffer, which receive the address signal ADDR and the command signal
`
`CMD, respectively. The second clock signal CLK2 serves to drive data buffers. Thus,
`
`the first clock signal CLK1 having a low frequency is used as the operating clock signal
`
`21
`21
`
`

`
`9
`
`of the address signal ADDR and the command signal CMD, and the second clock signal
`
`CLK2 having a high frequency is used to input/output data.
`
`The first clock signal CLK], the second clock signal CLK2, the address signal ADDR
`
`and the command signal CMD are supplied by a memory controller or microprocessor
`
`(not shown), and are connected to various devices, in particular, the memory module
`
`700, through bus lines running on the system board.
`
`FIG. 8 illustrates a modification of FIG. 7 and represents a first embodiment of the
`
`present invention. Here, the address signal ADDR and a command signal CMD output
`
`from a register 710 are connected to memory chips 701, 702,..., 706 from the center ofa
`
`memory module 700'. Accordingly, the address signal ADDR and the command signal
`
`CMD output from the register 710 are transmitted in two directions (center—to-lefi and
`
`center-to-right in FIG. 8) across the memory module 700 to the memory chips 70],
`
`702,..., 706. The configuration of this embodiment reduces a difference in line load to
`
`the memory chips 70], 702,
`
`, 706, and thereby reduces skew among the memory
`
`chips 710, 702,
`
`, 706.
`
`FIG. 9 illustrates another modification of FIG. 7. Here, the first clock signal CLKI and
`
`the second clock signal CLK2 are supplied by a phase locked loop (PLL) which
`
`receives a system clock signal CLK loaded on the system board, rather than by a
`
`memory controller or microprocessor.
`
`FIG. 10 illustrates a modification of FIG. 9 and represents a second embodiment of the
`
`present invention. Here, like in FIG. 8, the address signal ADDR and a command signal
`
`CMD output from a register 910 are connected to memory chips 901 , 902,..., 906 from
`
`the center of a memory module 900'. Accordingly, the address signal ADDR and the
`
`command signal CMD output from the register 910 are transmitted in two directions
`
`(center-to-lefi and center-to—right in FIG. 10) across the memory module 900 to the
`
`memory chips 901, 902,..., 906. The configuration of this embodiment reduces a
`
`difference in line load to the memory chips 901, 902,
`
`, 906, and thereby reduces
`
`skew among the memory chips 910, 902,
`
`, 906.
`
`22
`22
`
`

`
`10
`
`The memory modules shown in FIGS. 7 through 10 operate in substantially the same
`manner, which will now be described with reference to the memory module exemplified
`in FIG. 7. The frequency of the first clock signal CLK1 is lower than that of the second
`clock signal CLK2. The first clock signal CLK1 having the low frequency is used as
`the operating clock signal of the register 710, and the second clock signal CLK2 having
`the high frequency is used as the operating clock signals of the memory chips 701 ,
`702,..., 706, to thereby adapt the perfonnance of the register 710 operating at a
`relatively low speed, to the higher operating speeds of the memory chips 70], 702,...,
`706. The memory chips 701, 702,..., 706 may consist of high-speed synchronous
`DRAMS, for example, DDR DRAMS or SDR DRAMS.
`
`In contrast to the conventional memory module which receives a single clock signal and
`distributes the same throughout the memory module, the memory module 700 of the
`present invention receives two clock signals CLK1 and CLK2 and connects the same to
`devices operating at different frequencies, that is, the register 71 O and the memory chips
`701, 702,..., 706, respectively. Thus, the memory module 700 includes two module pins
`used to receive the two clock signals CLK1 and CLK2.
`
`In the memory modules 700, 700', 900 and 900' shown in FIGS. 7 through 10, since the
`registers and memory chips operating at different frequencies in the memory modules
`are selectively supplied with clock signals having the corresponding frequencies, the
`register having the relatively low operating frequency is operated in a stable manner.
`
`FIG. 11 depicts a memory module 1 100. The memory module 1100 is substantially the
`same as the memory module 700 shown in FIG. 7, except that in the present
`embodiment a phase lock loop 1 120 receives the second clock signal CLK2 and
`distributes the same to the memory chips 1101, 1102,..., 1106.
`
`In particular, the PLL 1120 receives the second clock signal CLK2 and generates a
`plurality ofintemal clock signals ICLKI, ICLK2,..., ICLK6, and transmits the same to
`the memory chips 1101, 1102,..., 1106. The internal clock signals ICLKI, ICLK2,...,
`ICLK6 have the same slew rate and duty cycle and approximate ideal signals without
`skew. Also, since the internal clock signals ICLKI, ICLK2,..., ICLK6 are synchronized
`
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`
`11
`
`with the second clock signal CLK2 in phase, they have the same frequency as the
`
`second clock signal CLK2. Thus, the internal clock signals ICLK1, ICLK2,..., ICLK6
`
`also have a high frequency.
`
`FIG. 12 illustrates a modification ofFIG. 1 1. Here, like in FIG. 8, the address signal
`
`ADDR and a command signal CMD output from a register 1110 are connected to
`
`memory chips 1 101, 1102,..., 1106 from the center ofa memory module 1100'.
`
`Accordingly, the address signal ADDR and the command signal CMD output from the
`
`register 1 110 are transmitted in two directions (center-to-lefi and center-to-right in FIG.
`
`12) across the memory module 1100’ to the memory chips 1101, ]lO2,..., 1106. The
`
`configuration of this embodiment reduces a difference in line load to the memory chips
`ll0l, 1 I02,
`, H06, and thereby reduces skew among the memory chips 1110, 1102,
`, 1106.
`
`In the memory modules 1100 and l 100’ shown in FIGS. 11 and 12, since the registers
`
`and memory chips operating at different frequencies in the memory modules are
`
`selectively supplied with clock signals having the corresponding frequencies, the
`
`register having the relatively low operating frequency is operated in a stable manner.
`
`Although specific embodiments of the invention have been described herein for
`
`illustrative purposes, various modifications and equivalents thereof can be made without
`
`departing from the spirit and scope of the invention, as will be recognized by those
`
`skilled in the relevant art. As one example only, it is noted that the invention has been
`
`described above as employing two clock signals, that is, the first clock signal CLK1 and
`
`the second clock signal CLK2. However, the memory module may also be configured
`
`to receive more than two clock signals having different operating frequencies which are
`
`then connected to various devices operating at different frequencies. Accordingly, the
`invention is not intended to be limited to the disclosure, but instead its scope is to be
`detennined entirely by the following claims.
`
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`
`CLAIMS:
`
`1.
`
`A system comprising:
`
`a plurality of bus lines which respectively transfer a first clock signal, a second
`
`clock signal, an address signal and a command signal, respectively, wherein a frequency
`
`of the first clock signal is different than a frequency of the second clock signal; and
`
`a memory module which is connected to the plurality of bus lines and which
`
`comprises (a) a register which is connected to the bus of the first clock signal, the bus of
`
`the address sigial, and the bus of the command sigial, and which stores the address
`
`signal and the command signal at a timing of the first clock signal, and (b) a plurality of
`
`memory chips which are each connected to the bus line of the second clock signal and
`
`which receives the address signal and command signal stored in the register at a timing
`of the second clock signal, wherein the address signal and the command signal are
`
`transmitted to the memory chips in two directions from a center of the memory module.
`
`2.
`
`The system according to claim 1, further comprising a memory controller which
`
`supplies the first clock sigial, the second clock signal, the address signal and the
`
`command signal.
`
`The system according to claim 1, wherein the frequency of the first clock sigial
`3.
`is lower than the frequency of the second clock siglal.
`
`4.
`The system according to claim 1, wherein the memory module includes at least
`two module pins which receive the first and second clock signals.
`
`5.
`
`A system comprising:
`
`a plurality ofbus lines which respectively transfer a system clock signal, an
`
`address signal and a command signal, respectively,
`
`a phase lock loop which receives the system clock signal and which outputs a
`
`first clock signal and a second clock signal, wherein a frequency of the first clock sigial
`is different than a frequency of the second clock sigial; and
`
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`'37
`
`a memory module which is connected to the plurality of bus lines and which
`
`comprises (a) a register which is connected to the bus of the first clock signal, the bus of
`
`the address signal, and the bus of the command signal, and which stores the address
`
`signal and the command signal at a timing of the first clock signal, and (b) a plurality of
`
`memory chips which are each connected to the bus line of the second clock signal and
`
`which receives the address signal and command signal stored in the register at a timing
`
`of the second clock signal, wherein the address signal and the command signal are
`
`transmitted to the memory chips in two directions from a center of the memory module.
`
`6.
`
`The system according to claim 5, fiirther comprising a memory controller which
`
`supplies the system clock signal, the address signal and the command signal.
`
`7.
`
`The system according to claim 5, wherein the frequency of the first clock signal
`
`is lower than the frequency of the second clock signal.
`
`8.
`
`The system according to claim 5, wherein the memory module includes at least
`
`two module pins which receive the first and second clock signals.
`
`9.
`
`A system comprising:
`
`a plurality of bus lines which respectively transfer a first clock signal, a second
`
`clock signal, an address signal and a command signal, respectively, wherein a frequency
`
`of the first clock signal is different than a frequency of the second clock signal; and
`
`a memory module which is connected to the plurality of bus lines and which
`
`comprises (a) a register which is connected to the bus of the first clock signal, the bus of
`
`the address signal, and the bus of the command signal, and which stores the address
`
`signal and the command signal at a timing of the first clock signal, (b) a phase locked
`
`loop which is connected to the bus of the second clock signal and which outputs a
`
`plurality of internal clock signals having a same frequency as the second clock signal,
`
`and (c) a plurality of memory chips which are each connected to the phase locked loop
`
`and which receives the address signal and command signal stored in the register at a
`
`timing of a respective one of the plurality of internal clock signals, wherein the address
`
`signal and the command signal are transmitted to the memory chips in two directions
`
`from a center of the memory module.
`
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`
`wt
`
`10.
`
`The system according to claim 9, further comprising a memory controller which
`
`supplies the first clock signal, the second clock signal, the address signal and the
`
`command signal.
`
`1 1.
`
`The system according to claim 9, wherein the frequency of the first clock signal
`
`is lower than the frequency of the second clock signal.
`
`12.
`
`The system according to claim 9, wherein the memory module includes at least
`
`two module pins which receive the first and second clock signals.
`
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